From patchwork Thu Aug 12 11:24:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 496756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B68FBC25AF1 for ; Thu, 12 Aug 2021 11:24:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8AAE660F91 for ; Thu, 12 Aug 2021 11:24:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236875AbhHLLZF (ORCPT ); Thu, 12 Aug 2021 07:25:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236823AbhHLLYy (ORCPT ); Thu, 12 Aug 2021 07:24:54 -0400 Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED573C061389 for ; Thu, 12 Aug 2021 04:24:27 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:438:1ff1:1071:f524]) by xavier.telenet-ops.be with bizsmtp id gbQR250161gJxCh01bQR3W; Thu, 12 Aug 2021 13:24:25 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mE8oz-002Fix-JI; Thu, 12 Aug 2021 13:24:25 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mE8ox-007449-R7; Thu, 12 Aug 2021 13:24:23 +0200 From: Geert Uytterhoeven To: Magnus Damm , Rob Herring Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Laurent Pinchart Subject: [PATCH v2 13/29] arm64: dts: renesas: Add support for H3ULCB with R-Car H3e Date: Thu, 12 Aug 2021 13:24:03 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the Renesas R-Car Starter Kit Premier equipped with an R-Car H3e SiP. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart --- v2: - Add Reviewed-by. --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a779m0-ulcb.dts | 53 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779m0-ulcb.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 69bdf8e92a459f1f..a18f9b9d2a335c78 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m0-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R8A77951) += r8a779m0-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779m0-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a779m0-ulcb.dts new file mode 100644 index 0000000000000000..57ae7866582f9a41 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779m0-ulcb.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) with R-Car H3e + * + * Copyright (C) 2021 Glider bv + * + * Based on r8a77951-ulcb.dts + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a779m0.dtsi" +#include "ulcb.dtsi" + +/ { + model = "Renesas H3ULCB board based on r8a779m0"; + compatible = "renesas,h3ulcb", "renesas,r8a779m0", "renesas,r8a7795"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x40000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x40000000>; + }; + + memory@700000000 { + device_type = "memory"; + reg = <0x7 0x00000000 0x0 0x40000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&versaclock5 3>, + <&versaclock5 4>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", "du.3", + "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; +};