From patchwork Wed Jul 21 08:39:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 483267 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp5988830jao; Wed, 21 Jul 2021 01:58:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTsvD+RKj1PKpeSu4KuKtNDu5jY1PccH2LlUtMnvPpOTSCZAOZLpGj7BjfVzsrWMMvP0LY X-Received: by 2002:a5e:d707:: with SMTP id v7mr11335000iom.46.1626857914585; Wed, 21 Jul 2021 01:58:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626857914; cv=none; d=google.com; s=arc-20160816; b=OWAY2v+NIp5Y6adN297JDZ/gpfukITYyP9a1woLc+cjTnzC+4qz77Zq8WVO6gLNKK7 iyGpeQe5ngZY5p9oKOsa2Ce4Zb7dEDakTQZoFJK1c/2R1QYAbHDKAsK6AmLJF1uxkO8j OeDKjpuRsktpnsOmq0xZCJH8X2gNlIRv1L0KvWLrOM8JM4gXtnJ5F8VVVrJZ8ldPoKBT AN1D+sq12CzJwKgwmhC0GxzWXrvUjQKPifp5UOUCe6JpQi01h1DLN5EEINoIkfqDqmHb 2AhovpbKIzgK/ackhKV+3un+74Tc31sdPz/Lujr5GGLe5bzeAQHpXOg2Y35kjag6xzGB 1RQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UDc4GdZdJMpvgCWtdJv7KQj8GnX0PhO4hBOrQhQRhw8=; b=sClajXJeJiOxjOAfAhuLlDVGXMO1GZLUuZAOqA8QGS/mm0hFATvC2xpVRw4mvIPiQo NnxpbHWZXgMSc6oYPgGDeJx4k4wkpUB0k7Xa/c4hOvE9FP4j3VKxccq7Po1uMvenQkc1 OW9ps08SvkZNcaR/oSjcjffJtnOrjpkITODfq5Q4h4VJvGyLVf9TelmRHzLd6PeyGia4 4bfbBoIEWeY67icoFNd/qS4O4jrbkFzEdREaio9kOSg9K0iIcIhVe5OdCBn+DPvIAKBZ ww/6uxa8A44ZniDBt9iLNiro/BNWv1UpV5yCeD95D6CMEI6ih4oiZpmyYL2HpUPbAVYN XS0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HE1psxCh; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v20si26601868jao.88.2021.07.21.01.58.34; Wed, 21 Jul 2021 01:58:34 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HE1psxCh; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236338AbhGUIRh (ORCPT + 7 others); Wed, 21 Jul 2021 04:17:37 -0400 Received: from mail.kernel.org ([198.145.29.99]:50692 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237189AbhGUH77 (ORCPT ); Wed, 21 Jul 2021 03:59:59 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7F0FC6120E; Wed, 21 Jul 2021 08:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626856759; bh=qppQeRmcGvRopw+qAp0appWXEfjJqS9op3P1nX7fpKw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HE1psxChELNcYD+pQFaPbsX6HWoNH6MbChbYD/U8PfJyE+1dSjVmIB2gfjpGaqSo2 EsAzC2GgmDL4SZ537gPH7unHcMaq7jBmAGP1li3VRwWHAtXuk79YqmTk0LkPFS2Uid wWpeZSs49ubTuz079OH/WoKZW7XdtiPcuibTarOVk2fiA+PLu2WEMW7JKdXWvKcGXQ 5lJQ8Ygv8kKLFnHWX6uN+LvSt5+w8rEpRlzndY75pd4rc+FvAaH/gSf53EYDsjBhNh 4hniAJxQNitvJbWf2XdB+X8HxsEdXwPAEpx8ByYN34awryL083C48QZFfJV5XDqWt8 aSTk9LoQKEIYg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m67l5-0022dm-LS; Wed, 21 Jul 2021 10:39:15 +0200 From: Mauro Carvalho Chehab To: Vinod Koul , Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam , =?utf-8?q?Krzysztof_Wilczy=C5=84s?= =?utf-8?q?ki?= , Binghui Wang , Lorenzo Pieralisi , Rob Herring , Wei Xu , Xiaowei Song , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH v7 08/10] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Date: Wed, 21 Jul 2021 10:39:10 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Manivannan Sadhasivam Add DTS bindings for the HiKey 970 board's PCIe hardware. Co-developed-by: Mauro Carvalho Chehab Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++ .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - drivers/pci/controller/dwc/pcie-kirin.c | 12 ---- 3 files changed, 71 insertions(+), 13 deletions(-) -- 2.31.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 1f228612192c..6dfcfcfeedae 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", + "aclk"; + + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, + <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi index 48c739eacba0..03452e627641 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */ regulator-name = "ldo33"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; }; ldo34: LDO34 { /* GPS AUX IN VDD */ diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index bfc0513f7b15..9dad14929538 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -347,18 +347,6 @@ static const struct regmap_config pcie_kirin_regmap_conf = { .reg_stride = 4, }; -/* Registers in PCIeCTRL */ -static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie, - u32 val, u32 reg) -{ - writel(val, kirin_pcie->apb_base + reg); -} - -static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) -{ - return readl(kirin_pcie->apb_base + reg); -} - static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) {