From patchwork Fri Jul 9 10:41:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 471807 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp156394jao; Fri, 9 Jul 2021 03:41:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqOh4YVxUWsK+o835jxNusg+6Ca0ZvxfVvma456g4Nx262pqkAb6wOnFo5z0rFAKcXKqoJ X-Received: by 2002:a17:907:2d0a:: with SMTP id gs10mr36339043ejc.207.1625827316535; Fri, 09 Jul 2021 03:41:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625827316; cv=none; d=google.com; s=arc-20160816; b=InYXknEnKXiGzdWXRrwCb0qQCwDpo98LkxubmoNEVhOXkeWFYNXROlJpJPRw0heAzt hoKXv88ilv3amcTwihHyskcxcTKomTZ/r4R3pKA7zyZcS6bcNnUZPZ2U00z2hf9LQ5TG gjcP4fXMN1wsxdqMcEZ1KjuGMvaVduLTeS9V5e0kXvZC5uyq12QM3pUdIuuyZkkGi8yK CB11CS0YskVW6jderK+2Cns9zFYrP08sVCSBu2fzBMiMdgn8Ehkm26S5hCEKYEBlPUnX jE0ijdbyoHGoBU11H7QCZzL7qGjYCOXOFwL5+yePE+TGD6vWUEXclbQACaEyKjCskXdU nA8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TBLCwNWq33mebLeTASjYZm8fJUHv4o+3j40sGp+O04Y=; b=NNTVXPYyzuJEO9SMx/TuvKP0yGzpdauyWq+uyjuGqkYO4Km3xwWtWgmoXJkIuSDOn8 A7gnZMq6e44Mxs+l7bF8o49k0i4RzcRVIbCXD3JUFGNMStfK1uD/DWGMQcorIpN2mMts 98vucUaWXz07B+9L8D5+eJBIFfDRgZhX2WEr385K3a9SJR83YSbNA8KPElKyMerC/NKB oGjdn97sz2HBs9ElcWX7ls9JYktCj9o/vIhZDwvKbGHT4SVFcadExM4d5cyQTlPN1jwF fNwTSXT7GZ4cBgqLA1A5wcd4vApdu9Y6BbfccNnDW24fxTK7qHKkyB5xmHVZz6bVksZk 5+0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=SslcZji1; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id f11si6464978ejk.138.2021.07.09.03.41.56; Fri, 09 Jul 2021 03:41:56 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=SslcZji1; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230164AbhGIKoh (ORCPT + 7 others); Fri, 9 Jul 2021 06:44:37 -0400 Received: from mail.kernel.org ([198.145.29.99]:47544 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230000AbhGIKoe (ORCPT ); Fri, 9 Jul 2021 06:44:34 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5EA19613F0; Fri, 9 Jul 2021 10:41:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625827311; bh=m59H58S8c6uJmUxjlwS9k0tBdkqFiZIxmvII33/F3pI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SslcZji14eYszw8cDvpsfM8KITDXGg+CWncX5fUuz0NXcIxEYebukwcpftPMSPKsi OJQaVqH/hzX9FY6T/BH1nwFf65zUpB4XhdGAnHLHCry2Vd0MUpEr1/gojp/fYU0Bpp zdy+HKeWUoFzTuf8FACkfnSKhZ9AQoDsAzssUP/baWB1xYx2RmDpPb6/W4zNnhcoCl bXDraS2bm3x4+0hDcMSKO6HmUzK/Dl5Rc1h7wimkUCTqWl5zfyuDha+8M8w2GRwTHi 50EmuXR3PcvLwUpyjzjawpFPOqxkOOd1yOGnzUxJsYeMjdw+RN5ISbSVQtLQnV1LmA d4ApfW5g5CCwQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m1nx7-00B5G4-LF; Fri, 09 Jul 2021 12:41:49 +0200 From: Mauro Carvalho Chehab To: Manivannan Sadhasivam , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam , Rob Herring , Wei Xu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH v3 9/9] arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware Date: Fri, 9 Jul 2021 12:41:45 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Manivannan Sadhasivam Add DTS bindings for the Hikey 970 board's PCIe hardware. Co-developed-by: Mauro Carvalho Chehab Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 72 +++++++++++++++++++ .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - 2 files changed, 72 insertions(+), 1 deletion(-) -- 2.31.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 6476149d99e3..f54dab70f01b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,72 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + reg-names = "phy"; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, + <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi index 48c739eacba0..03452e627641 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */ regulator-name = "ldo33"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; }; ldo34: LDO34 { /* GPS AUX IN VDD */