From patchwork Fri Jul 9 10:41:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 472024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A167C11F6C for ; Fri, 9 Jul 2021 10:41:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00A32613D6 for ; Fri, 9 Jul 2021 10:41:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230372AbhGIKoj (ORCPT ); Fri, 9 Jul 2021 06:44:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:47704 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230024AbhGIKog (ORCPT ); Fri, 9 Jul 2021 06:44:36 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 38B9A613E8; Fri, 9 Jul 2021 10:41:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625827313; bh=Wbz8BIqkDGOGe5Y5QXz3JddAMSpth4TA47h5iTOOx2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sPQ17iO9T6VggNrBhlpXzDCb5hK5vS/GJIskbl3lFNvECA6eO7gtZmzSZFsLKSeF9 Rk2KbgAA9OGcAAzeCXjMHLT3iu4W1ZOfT+QbkBKznuUp27T9Loq89MZ2YE2gjjrS8B hSKmRaRokYv5weAr++FwQHNY4lZyktgWz0/Hh+d4pEe9TbyXXtr3Srfk8On+zRlDBb XzUSX9QEUsXpmFMU5+6NuiBYO/E4R54/80C5yJ9ZUwc1tOa/h0EA2xUYQkLxc0vXs1 rrBtO2L7l3c283uGK1gUhJcopaveApsAD1c6Itb2B45tDbiQFEGCim7H+mXDKJD8In hWe8CIb1SGNOg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m1nx7-00B5FS-4z; Fri, 09 Jul 2021 12:41:49 +0200 From: Mauro Carvalho Chehab To: Manivannan Sadhasivam , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Rob Herring , Vinod Koul , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 1/9] dt-bindings: phy: add bindings for Hikey 960 PCIe PHY Date: Fri, 9 Jul 2021 12:41:37 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings for Hikey 960 (hi3660) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3660-pcie.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml new file mode 100644 index 000000000000..bed290059abb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3660-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kirin960 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 960. + +properties: + compatible: + const: hisilicon,hi960-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: pcie_phy_ref + - const: pcie_aux + - const: pcie_apb_phy + - const: pcie_apb_sys + - const: pcie_aclk + + reset-gpios: + description: PCI PERST reset GPIO + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + }; +...