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[2001:1868:205::9]) by mx.google.com with ESMTPS id f33si9727957qgf.0.2014.04.16.13.20.18 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Apr 2014 13:20:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WaWIH-000869-8l; Wed, 16 Apr 2014 20:18:53 +0000 Received: from mail-qg0-f42.google.com ([209.85.192.42]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WaWIF-000818-BH for linux-arm-kernel@lists.infradead.org; Wed, 16 Apr 2014 20:18:52 +0000 Received: by mail-qg0-f42.google.com with SMTP id q107so12082224qgd.29 for ; Wed, 16 Apr 2014 13:18:28 -0700 (PDT) X-Received: by 10.140.29.130 with SMTP id b2mr12584359qgb.48.1397679507765; Wed, 16 Apr 2014 13:18:27 -0700 (PDT) Received: from xanadu.home (modemcable177.143-130-66.mc.videotron.ca. [66.130.143.177]) by mx.google.com with ESMTPSA id z8sm45301398qaw.17.2014.04.16.13.18.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 16 Apr 2014 13:18:27 -0700 (PDT) Date: Wed, 16 Apr 2014 16:18:25 -0400 (EDT) From: Nicolas Pitre To: Abhilash Kesavan Subject: Re: [PATCH 1/5] ARM: bL_switcher: Don't enable bL switcher on systems without CCI In-Reply-To: Message-ID: References: <1397239311-27717-1-git-send-email-a.kesavan@samsung.com> <1397239311-27717-2-git-send-email-a.kesavan@samsung.com> User-Agent: Alpine 2.11 (LFD 23 2013-08-11) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140416_131851_528761_626AC5B2 X-CRM114-Status: GOOD ( 34.08 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.42 listed in list.dnswl.org] Cc: "mark.rutland" , devicetree , Lorenzo Pieralisi , Arnd Bergmann , Andrew Bresticker , Tomasz Figa , inderpal.s@samsung.com, Will Deacon , robh+dt , Thomas P Abraham , Grant Likely , Kukjin Kim , Dave Martin , linux-arm-kernel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nicolas.pitre@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On Thu, 17 Apr 2014, Abhilash Kesavan wrote: > Hi Nicolas, > > On Fri, Apr 11, 2014 at 11:44 PM, Nicolas Pitre > wrote: > > On Fri, 11 Apr 2014, Abhilash Kesavan wrote: > > > >> From: Andrew Bresticker > >> > >> Do not enable the big.LITTLE switcher on systems that do not have an > >> ARM CCI (cache-coherent interconnect) present. Since the CCI is used > >> to maintain cache coherency between multiple clusters and peripherals, > >> it is unlikely that a system without CCI would support big.LITTLE. > >> > >> Signed-off-by: Andrew Bresticker > >> Signed-off-by: Abhilash Kesavan > > > > The b.L switcher depends on MCPM, and it also expects only 2 clusters > > which is evaluated at run time or it bails out. > > > > There might be in theory other ways than the CCI to enforce coherency > > between clusters. And that should all be encapsulated by the MCPM > > layer. The switcher module should not be concerned at all by the > > underlying hardware mechanism. > > > > So if the goal is to determine at run time whether or not the switcher > > should be activated in a multi-config kernel, then the criteria should > > be whether or not MCPM is initialized, and not if there is a CCI. > > Yes, we have a multi-SoC enabled kernel (with MCPM and BL_SWITCHER > configs enabled); one SoC has a single cluster while the other is a > dual cluster. We wanted a run-time check to prevent bL_switcher from > running on the single cluster one and zeroed in on CCI. But, I get > your point as to why CCI should not be used as a distinguishing factor > for switcher initialization. > > For now, I can use the no_bL_switcher parameter to disable it on > certain platforms. However, can you elaborate on the MCPM > initialization check you suggested ? Here's what I mean: ----- >8 From: Nicolas Pitre Date: Wed, 16 Apr 2014 15:43:59 -0400 Subject: [PATCH] ARM: bL_switcher: fix validation check before its activation The switcher should not depend on MAX_CLUSTER which is a build time limit to determine ifit should be activated or not. In a multiplatform kernel binary it is possible to have dual-cluster and quad-cluster platforms configured in. In that case MAX_CLUSTER should be 4 and that shouldn't prevent the switcher from working if the kernel is booted on a b.L dual-cluster system. In bL_switcher_halve_cpus() we already have a runtime validation check to make sure we're dealing with only two clusters, so booting on a quad cluster system will be caught and switcher activation aborted. However, the b.L switcher must ensure the MCPM layer is initialized on the booted hardware before doing anything. The mcpm_is_available() function is added to that effect. Signed-off-by: Nicolas Pitre diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c index 5774b6ea7a..f01c0ee0c8 100644 --- a/arch/arm/common/bL_switcher.c +++ b/arch/arm/common/bL_switcher.c @@ -797,10 +797,8 @@ static int __init bL_switcher_init(void) { int ret; - if (MAX_NR_CLUSTERS != 2) { - pr_err("%s: only dual cluster systems are supported\n", __func__); - return -EINVAL; - } + if (!mcpm_is_available()) + return -ENODEV; cpu_notifier(bL_switcher_hotplug_callback, 0); diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c index 1e361abc29..86fd60fefb 100644 --- a/arch/arm/common/mcpm_entry.c +++ b/arch/arm/common/mcpm_entry.c @@ -48,6 +48,11 @@ int __init mcpm_platform_register(const struct mcpm_platform_ops *ops) return 0; } +bool mcpm_is_available(void) +{ + return (platform_ops) ? true : false; +} + int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster) { if (!platform_ops) diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h index 608516ebab..a5ff410dcd 100644 --- a/arch/arm/include/asm/mcpm.h +++ b/arch/arm/include/asm/mcpm.h @@ -54,6 +54,13 @@ void mcpm_set_early_poke(unsigned cpu, unsigned cluster, */ /** + * mcpm_is_available - returns whether MCPM is initialized and available + * + * This returns true or false accordingly. + */ +bool mcpm_is_available(void); + +/** * mcpm_cpu_power_up - make given CPU in given cluster runable * * @cpu: CPU number within given cluster