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Sat, 26 Aug 2023 12:24:24 +0000 From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Inochi Amaoto , Heiko Stuebner , Wei Fu , Pei Chen , Guo Ren Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] riscv: dts: allwinner: d1: Add PMU event node Date: Sat, 26 Aug 2023 20:25:04 +0800 Message-ID: X-Mailer: git-send-email 2.41.0 X-TMN: [RYzYcXWKkeYnCjJlXZCx8/HAnwHN3S6TFjU8lyuOsPU=] X-ClientProxiedBy: SI1PR02CA0030.apcprd02.prod.outlook.com (2603:1096:4:1f4::8) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20230826122504.294619-1-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|MW3PR20MB3515:EE_ X-MS-Office365-Filtering-Correlation-Id: fdfe73b8-18a7-4e8b-72b5-08dba62f61e2 X-MS-Exchange-SLBlob-MailProps: Om8TgR6f4EB/EQr+q11q+JsAPQ9zfesvHLrCWlIfvFrsW/v3HtS2Vcml9bmeeex43BWSzgefz4FDpGKn1WISdOA8QqXGeLicSY4GWDwIbtic1XNOEH9ioYsm1UYYzxM1ncbeAqSYnk2LtUkF2LGnr8WUraOmSp33V0XBs5t4j/Irbw1ZnBgxkXYJmRT2x5Z0svPyzbGZk5sELLO84VBjXeRGL57vbxbNLp+cwXlDvVQXovGejztHR8WYDYzuT1kZ9DlUFd8m5D7OPuXBZpw5Fkokb8PgSVqUNS6EF7q2m3LypMzW51uwI+2TJpYoAeP4E3wnDF8BcjlFupljrDWoG5Es9G0VJ+wZSdjTjj5Tj4Lyg9RjI6ujOQpQxiejb3p9h6rSnSPqY9PZogzEvVgGBVgmyvVfysMNpxLmQpYiRVHa+Pn2mrfI+b8GpY/RxvlCT5/W9uDCz8R/93Lx8HZcTmrmo2C8KRoBe9EC5hkIlCtUoOHwcuHeQdCJJCYM5wNw/mnJSU/+e+kzaQabLtXFidUikjvTSd5+gC72/VnlCH+OLVtjPiVjaNZ2rsmH2BedubCiWBK9sbcjYuL/CflhNqd6lwtR2EiOHHEr2X0DdZT6jrx3zzJ5y7Al+fkdVqXqJ0KMkA+1RObZUHt+vCl5+wvtdJUCakwcHc1QcBa1ma/81RpCrv5yQfRQPih7tRnY9T2GJJAB9r84bERCbCrlMHVO7ngW7tqq3tl2M1U7DfV8QXKX9nxOSqYGCkiR26MzqSQduyajbPCpu1gevcb7WBifODhh+d6rBIUQnoaQAY8LUZZaLEipe5DUW8adxl9KPkKTa9CfVU0pqXovaqNpwFY6NjKsw9aB X-Microsoft-Antispam: BCL:0; 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These events can be used by perf for profiling. The event value and mapping can be found in the R1S0 version of C906 documentation: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Signed-off-by: Inochi Amaoto --- The meaning of T-HEAD events can be found in this pending patch: https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com The patch above also provides a detailed example that shows how to setup environment and use perf with T-HEAD events. --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) -- 2.41.0 diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 8275630af977..d9031ccdec89 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -72,5 +72,45 @@ plic: interrupt-controller@10000000 { #address-cells = <0>; #interrupt-cells = <2>; }; + + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = + <0x00003 0x00003 0x00000008>, + <0x00004 0x00004 0x00000010>, + <0x00005 0x00005 0x00000200>, + <0x00006 0x00006 0x00000100>, + <0x10000 0x10000 0x00004000>, + <0x10001 0x10001 0x00008000>, + <0x10002 0x10002 0x00010000>, + <0x10003 0x10003 0x00020000>, + <0x10019 0x10019 0x00000040>, + <0x10021 0x10021 0x00000020>; + riscv,event-to-mhpmevent = + <0x00003 0x00000000 0x00000001>, + <0x00004 0x00000000 0x00000002>, + <0x00005 0x00000000 0x00000007>, + <0x00006 0x00000000 0x00000006>, + <0x0000a 0x00000000 0x0000000b>, + <0x10000 0x00000000 0x0000000c>, + <0x10001 0x00000000 0x0000000d>, + <0x10002 0x00000000 0x0000000e>, + <0x10003 0x00000000 0x0000000f>, + <0x10019 0x00000000 0x00000004>, + <0x10021 0x00000000 0x00000003>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; + }; }; };