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Sun, 27 Aug 2023 06:44:19 +0000 From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Inochi Amaoto , Heiko Stuebner , Wei Fu , Pei Chen , Wenhan Chen , Guo Ren Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] riscv: dts: allwinner: d1: Add PMU event node Date: Sun, 27 Aug 2023 14:45:01 +0800 Message-ID: X-Mailer: git-send-email 2.42.0 X-TMN: [eG0EICRNxrDhs226+QL68iyFWVEBi3em0O6KXS/w6p8=] X-ClientProxiedBy: TYAPR01CA0019.jpnprd01.prod.outlook.com (2603:1096:404::31) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20230827064501.392205-1-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|DS0PR20MB5757:EE_ X-MS-Office365-Filtering-Correlation-Id: 38bbe6e6-88e3-4ec8-ee1e-08dba6c909c6 X-MS-Exchange-SLBlob-MailProps: cn60g5V53KNKBQSRra15jT4jAkk0OqZJ1BeJTn3sqKn7TtKOvZ/DsauzV2I3NaGLTdkcckoThhvU8zSAaAR8bmriPfM3+Zj9aIYyTDgUIksUgNocMqi741hmn05F49P3nNiCO9rN/McT8ot4L6YAiy2VqM7WpCUDc91TojAL4krzVIjrxOe0m7EfP9FbsE01GiO3jJJoccdADXpBNm1xK98OsfPdbs7EWWEhi7sbf7nk7Ru+DU2ecp5IMlxUfZTC0kNr4bnBh/HFCyKoPHyrycz6LScpZYL2am7KqSLuhvzH1sMLwDKfaO98aUDFB5jHu8NON+On8O5rPsHBfkwN0Lc2uRMNOF6QyjMP2OX+yGK45lvKcQjwjIb4d5qsOVigWQKI0VrCW8lxS5mWBCraCsDIsyCIwlTpJ9guepJJ5LfGRVCCZZsPZq+y4z2puBE8SRA51PdCczukm7TbLHJ/MRCWRsoXtIni2uvh8Sw9azo4fPiPF/NcmAKDXdApgrQgE4RLgnQZtv417pPTTpjwklaLJAOyuKrpMAYmVJjefJlD6Q1ur0rWJC9Lcsi4wLLfTVgOwFCjVh1pcBqXj5cx0FtqAmFbgSJYQou5xIq1CvRttWhtHQtvW7WAqavl5GWT4MER39LU8+CrrsRfTfwTu5XIY0iJ0ZagtjIctbHhnQyeMxAHNj/oanTA1tRAQB7OFjrCJZk54M6k7koVjWn2RNL/+F+391SFXLiF5woWvaQOqnmBp6vHlTXed4hNcS0SAxYzydHpbEVMe+oVaZr9qXnIiPzGHf07uBBigZmN5rd/bWB2CPEW3LD63l9fDmJphg0SCTKSGO6PQ86V6ATdsT8NzbKdH63jLn6To1CB55lHBGmCP2qc1A== X-Microsoft-Antispam: BCL:0; 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These events can be used by perf for profiling. Signed-off-by: Inochi Amaoto Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf --- changed from v2: 1. move pmu node from /soc to / to avoid warnings when cheching. The meaning of T-HEAD events can be found in this pending patch: https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com The patch above also provides a example that shows how to setup environment and use perf with T-HEAD events. --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) -- 2.42.0 diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 8275630af977..ed981af63b55 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -73,4 +73,44 @@ plic: interrupt-controller@10000000 { #interrupt-cells = <2>; }; }; + + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = + <0x00003 0x00003 0x00000008>, + <0x00004 0x00004 0x00000010>, + <0x00005 0x00005 0x00000200>, + <0x00006 0x00006 0x00000100>, + <0x10000 0x10000 0x00004000>, + <0x10001 0x10001 0x00008000>, + <0x10002 0x10002 0x00010000>, + <0x10003 0x10003 0x00020000>, + <0x10019 0x10019 0x00000040>, + <0x10021 0x10021 0x00000020>; + riscv,event-to-mhpmevent = + <0x00003 0x00000000 0x00000001>, + <0x00004 0x00000000 0x00000002>, + <0x00005 0x00000000 0x00000007>, + <0x00006 0x00000000 0x00000006>, + <0x0000a 0x00000000 0x0000000b>, + <0x10000 0x00000000 0x0000000c>, + <0x10001 0x00000000 0x0000000d>, + <0x10002 0x00000000 0x0000000e>, + <0x10003 0x00000000 0x0000000f>, + <0x10019 0x00000000 0x00000004>, + <0x10021 0x00000000 0x00000003>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; + }; };