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Thu, 28 Dec 2023 13:07:08 +0000 Received: from DM6PR20MB2316.namprd20.prod.outlook.com ([fe80::1d59:b3c8:8763:a672]) by DM6PR20MB2316.namprd20.prod.outlook.com ([fe80::1d59:b3c8:8763:a672%4]) with mapi id 15.20.7113.028; Thu, 28 Dec 2023 13:07:08 +0000 From: AnnanLiu To: chao.wei@sophgo.com, unicorn_wang@outlook.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, AnnanLiu Subject: [PATCH] riscv: dts: sophgo: add timer dt node for CV1800 Date: Thu, 28 Dec 2023 21:06:54 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 X-TMN: [FZcb8sp6ZVtinXhxXjQ72aB2YRAr4unhFRBjEJCLz+o=] X-ClientProxiedBy: TYAPR01CA0167.jpnprd01.prod.outlook.com (2603:1096:404:7e::35) To DM6PR20MB2316.namprd20.prod.outlook.com (2603:10b6:5:1a8::28) X-Microsoft-Original-Message-ID: <20231228130654.182008-1-annan.liu.xdu@outlook.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6PR20MB2316:EE_|IA1PR20MB6432:EE_ X-MS-Office365-Filtering-Correlation-Id: 13d2b8be-928c-4ace-c5ba-08dc07a5e568 X-Microsoft-Antispam: BCL:0; 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This patch depends on the clk driver and reset driver. Clk driver link: https://lore.kernel.org/all/IA1PR20MB49539CDAD9A268CBF6CA184BBB9FA@IA1PR20MB4953.namprd20.prod.outlook.com/ Reset driver link: https://lore.kernel.org/all/20231113005503.2423-1-jszhang@kernel.org/ Signed-off-by: AnnanLiu --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 72 +++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index aec6401a467b..34a1647cc51b 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -113,6 +113,78 @@ plic: interrupt-controller@70000000 { riscv,ndev = <101>; }; + timer0: timer@030a0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0000 0x14>; + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer@030a0014 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0014 0x14>; + interrupts = <80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@030a0028 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0028 0x14>; + interrupts = <81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER2>; + status = "disabled"; + }; + + timer3: timer@030a003c { + compatible = "snps,dw-apb-timer"; + reg = <0x030a003c 0x14>; + interrupts = <82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER3>; + status = "disabled"; + }; + + timer4: timer@030a0050 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0050 0x14>; + interrupts = <83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER4>; + status = "disabled"; + }; + + timer5: timer@30a0064 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0064 0x14>; + interrupts = <84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER5>; + status = "disabled"; + }; + + timer6: timer@030a0078 { + compatible = "snps,dw-apb-timer"; + reg = <0x030a0078 0x14>; + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER6>; + status = "disabled"; + }; + + timer7: timer@030a008c { + compatible = "snps,dw-apb-timer"; + reg = <0x030a008c 0x14>; + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + resets = <&rst RST_TIMER7>; + status = "disabled"; + }; + clint: timer@74000000 { compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; reg = <0x74000000 0x10000>;