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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB73.mail.protection.outlook.com (10.167.242.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.13 via Frontend Transport; Mon, 8 Jan 2024 15:41:48 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 8 Jan 2024 09:41:17 -0600 From: Michal Simek To: , , , CC: Tejas Bhumkar , Conor Dooley , Krzysztof Kozlowski , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ZYNQ ARCHITECTURE" Subject: [PATCH 11/14] arm64: zynqmp: Disable Tri-state for MIO38 Pin Date: Mon, 8 Jan 2024 16:39:22 +0100 Message-ID: <9f8a0687be407a8ffad610087074e94ebc4f5982.1704728353.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; 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Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5809 From: Tejas Bhumkar gpio38 is used in SOM's kv260 to reset the Ethernet PHY. At present, HW reset is not working properly as Tri-state  is enabled for MIO38, causing inappropriate PHY register reads. Disabled Tri-state for MIO38 to make HW reset work. Tri-state disable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7a3 00000540 Tri-state enable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7e3 00000540 Signed-off-by: Tejas Bhumkar Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 25 +++++++++++++++++++ .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 25 +++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index b7b94254cc09..585b5845a1f4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -169,6 +169,25 @@ phy0: ethernet-phy@1 { &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -324,6 +343,12 @@ mux { }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 1446c2b19de7..037f0941ba0b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -152,6 +152,25 @@ phy0: ethernet-phy@1 { &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -307,6 +326,12 @@ mux { }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default";