From patchwork Tue Dec 5 15:10:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 120671 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5864067qgn; Tue, 5 Dec 2017 07:10:42 -0800 (PST) X-Google-Smtp-Source: AGs4zMbVK8Z21EqtpYghZPHRfPcajywgslxf04+xvPAz9/lUhPMvqAqCo2vh2ixQvF+n97hPU+kg X-Received: by 10.98.205.5 with SMTP id o5mr23271299pfg.39.1512486642231; Tue, 05 Dec 2017 07:10:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512486642; cv=none; d=google.com; s=arc-20160816; b=g6uBRzchrb1P1nkUqQbwzYA65biSQrt1zwH6WIb1m3mh1rd90KB6ejVG1oPDescqoF TnIstx3ojlyOb5UkdoRrxGsCLoO4I2aprnP3Yqzsm43XvedeweCrdU2iHqKMyoC01LUP 1Ptl5o2dGsdVb3NsFbpZed6WJTY9iTvoXORHiLGISSUgjuadpACg0L1Vl0hgWmk74t0q zToC60thyNgav3YDMLStHsV+oGDjkxKVRo/LRZr+r69k6M23kwPXAFKqO0vXUlZ6gz2/ ca3nKdG+ifPkFm9qLHhQf5ozdvEjwpMFjaR3W4waIjA2viOqPrCi2Y9+xmWxuXwKvv2H ucew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=JPAP/bv1t7sWrLo0pPRw2M7EprABBbKvh5WjnOlx/XY=; b=bYkSjXFCWOsghUb1zdvkiENT8t9OAPynT3L3j8sYNPiXtEMTDPo8vkn1zz8eK2LyPS x98x5XDkszY+F7yyExkk55u/EOy7T02iw1Gxf+zrILahmh8ClftGgjq/aR2fiXR9Zjrt r+HWadD23ozS53bCqQ2Y0wQb7JPaG2C7JbrnCS/688mNU01mm85cmJUGBsHvqQzAKj3x nHlyqYyOQQCZei/LFEhT0KIFYKHkEdu1HvMaQbb7BebAGDiY3CvDj4HnZ8DsgHalsFbt H8A4hElfd1vZLcA/N02MrCKTDX56RzAbE6erXoOv7bGXgOoyyF9VEZzWaVJwaduwrxSk EgVA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w12si198503pld.479.2017.12.05.07.10.42; Tue, 05 Dec 2017 07:10:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752858AbdLEPKk (ORCPT + 6 others); Tue, 5 Dec 2017 10:10:40 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:56074 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752841AbdLEPKi (ORCPT ); Tue, 5 Dec 2017 10:10:38 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 3C2F520739; Tue, 5 Dec 2017 16:10:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 0B5DD203A2; Tue, 5 Dec 2017 16:10:36 +0100 (CET) From: Maxime Ripard To: Daniel Vetter , David Airlie , Chen-Yu Tsai , Maxime Ripard Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Mark Rutland , Rob Herring , linux-arm-kernel@lists.infradead.org, plaes@plaes.org, icenowy@aosc.io, Thomas Petazzoni , jernej.skrabec@siol.net, devicetree@vger.kernel.org Subject: [PATCH v3 10/15] ARM: dts: sun8i: a83t: Add display pipeline Date: Tue, 5 Dec 2017 16:10:22 +0100 Message-Id: <97d3cee9d0d7a92893f646d72643bac520de5f05.1512486553.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The display pipeline on the A83T is mainly composed of the mixers and TCONs, plus various encoders. Let's add the first mixer and TCON to the DTSI since the only board I have can use only the LVDS output on the first TCON. The other parts will be added eventually. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 79 ++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+) -- git-series 0.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Chen-Yu Tsai diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 19acae1b4089..e4db38c717d9 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -45,8 +45,10 @@ #include #include +#include #include #include +#include #include / { @@ -151,6 +153,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-a83t-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + memory { reg = <0x40000000 0x80000000>; device_type = "memory"; @@ -162,6 +170,44 @@ #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-a83t-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_PLL_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + syscon: syscon@1c00000 { compatible = "allwinner,sun8i-a83t-system-controller", "syscon"; @@ -177,6 +223,39 @@ #dma-cells = <1>; }; + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-a83t-tcon-lcd"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-a83t-mmc", "allwinner,sun7i-a20-mmc";