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Wed, 20 May 2020 11:44:36 +0000 From: To: , , , , , Subject: [PATCH v9 1/2] PCI: Microchip: Add host driver for Microchip PCIe controller Thread-Topic: [PATCH v9 1/2] PCI: Microchip: Add host driver for Microchip PCIe controller Thread-Index: AQHWLpwJ9kFP6Hrw2k6pRUSXUoHryw== Date: Wed, 20 May 2020 11:44:36 +0000 Message-ID: <5dc3002680da40400b083748329d8b736219952e.camel@microchip.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: thegoodpenguin.co.uk; dkim=none (message not signed) header.d=none; thegoodpenguin.co.uk; dmarc=none action=none header.from=microchip.com; x-originating-ip: [89.101.219.210] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e95bfd6e-260c-4dac-1647-08d7fcb32c08 x-ms-traffictypediagnostic: MN2PR11MB3872: x-microsoft-antispam-prvs: x-bypassexternaltag: True x-ms-oob-tlc-oobclassifiers: OLM:3968; x-forefront-prvs: 04097B7F7F x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: Kpbs5yU0dHclxOmAhUFYuGV8w1JpecXKhKjpMWIKwNa47VzbBA+GySCIV54PZH7Zi1ShRA2tc8dGLoR8ecced2kCFBpkpC3EpxX6jjh2WQBORMHMSL4pN+MtE4UYcYTxqjTRkSAeA/S0YDR2QX8T794CzUNTaqn9zjgX5H9j4zc1Wzpz96l1WU4jDiXLVYWCCvfXotAmv9U2LjKPC4wyfA7oTFxwflBmdLIwoLbP6XXMUBlWc34cjGt0DSYjXz8BRf+Wta6RRxXysulRDSifibKDBeVmIBsZ6NUn2u9ZOZcTQDcuVUyvwr4wk7Pv8ZkwoRqiW/05GTHjnCGHOF72Gvp+2bSlM6m171tQbYBrrOEka+dQ3gwjmFR6mGonhk+k5ChnZMufoTlfI/D04/g5qvnavtBZysgskjZf2osGnKtkoWOWK7hUIw2vMSQ3pDXvOPVzibcB4sLapRep+iXWyBjqWdDWLcu7X0enlz7JBtCDYfJsA0vvdOgkuEGD8blN x-ms-exchange-transport-forked: True Content-ID: <227766FBC80D0A4FABC282A6D2B086F1@namprd11.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: e95bfd6e-260c-4dac-1647-08d7fcb32c08 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 May 2020 11:44:36.2998 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: j3+CywG7W01pR5gw4xj2pwkjk3pW+7ofNcfdAzrCNvRl2gY6QXKty1fpLjTXaDXjRA7Vb7aRJu6SexcWN/4jLXdMhZilC7xR9qAd6HDL+Us= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3872 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds device tree bindings for the Microchip PCIe PolarFire PCIe controller when configured in host (Root Complex) mode. Signed-off-by: Daire McNamara --- .../bindings/pci/microchip,pcie-host.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml new file mode 100644 index 000000000000..d3bcdab282c2 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PCIe Root Port Bridge Controller + +maintainers: + - Daire McNamara + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: microchip,pcie-host-1.0 # PolarFire + + reg: + maxItems: 2 + + reg-names: + items: + - const: cfg + - const: apb + + interrupts: + minItems: 1 + maxItems: 1 + items: + - description: PCIe host controller and builtin MSI controller + + interrupt-names: + minItems: 1 + maxItems: 1 + items: + - const: pcie/msi + + ranges: + maxItems: 1 + + dma-ranges: + maxItems: 1 + + msi-controller: + description: Identifies the node as an MSI controller. + + msi-parent: + description: MSI controller the device is capable of using. + +required: + - reg + - reg-names + - dma-ranges + - "#interrupt-cells" + - interrupts + - interrupt-names + - interrupt-map-mask + - interrupt-map + - msi-controller + +examples: + - | + soc { + pcie0: pcie@2030000000 { + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + compatible = "microchip,pcie-host-1.0"; + device_type = "pci"; + bus-range = <0x00 0x7f>; + // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(1) + interrupt-map = <0 0 0 1 &pcie0 0>, + <0 0 0 2 &pcie0 1>, + <0 0 0 3 &pcie0 2>, + <0 0 0 4 &pcie0 3>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&plic0>; + interrupts = <32>; + + // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) + ranges = <0x03000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + + // CPU_PHYSICAL(2) SIZE(2) + reg = <0x20 0x30000000 0x0 0x4000000>, + <0x20 0x0 0x0 0x100000>; + reg-names = "cfg", "apb"; + msi-parent = <&pcie0>; + msi-controller; + interrupt-controller; + }; + }; +...