From patchwork Fri Feb 28 13:58:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 204055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94F3FC3F2CD for ; Fri, 28 Feb 2020 13:58:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6C91F2051A for ; Fri, 28 Feb 2020 13:58:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="ZaecqM0n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726748AbgB1N6b (ORCPT ); Fri, 28 Feb 2020 08:58:31 -0500 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.80]:14830 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726642AbgB1N6b (ORCPT ); Fri, 28 Feb 2020 08:58:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582898308; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=Lg2vjJyPeK3SdOkL22G/V755a2Cx89sCodyhANXZ7FE=; b=ZaecqM0nrZ1pntXILB9tp0ZDdg9DJ6VndQrMNVCos3hB36cEL8Y7AJ6Pc9FOYBCZeF 1V8d573NglW9+mViklC+GrYS8tfO8lj6SViiFDyqIXIU3ZwvJfVlbJm0Jr30t0rvbvyl 2UDHRpcLjxFM/DUe8rHd4wAWdtIZ809rUODs5tRa0v+tuPM5nhK5MlffFouMMUjj1NO0 5+y7NvX2PB3wwy2Cy0WmjX83P+9cVlhS2jy18SIKUrwJk6fWA7NajqcOTOKIpYRZEsDq 7ANTgDcVnklV34gHecoTTP4M7RdBl1uYJv2O8wrTEu4IY3s6gqqW0dTVrX+DT1IUZp3v j7vw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6G1+ULkA=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.2.0 DYNA|AUTH) with ESMTPSA id y0a02cw1SDwP1A5 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Fri, 28 Feb 2020 14:58:25 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v7 1/7] memory: jz4780_nemc: Only request IO memory the driver will use Date: Fri, 28 Feb 2020 14:58:17 +0100 Message-Id: <551a8560261543c1decb1d4d1671ec4b7fa52fdb.1582898302.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paul Cercueil The driver only uses the registers up to offset 0x54. Since the EFUSE registers are in the middle of the NEMC registers, we only request the registers we will use for now - that way the EFUSE driver can probe too. Tested-by: H. Nikolaus Schaller Signed-off-by: Paul Cercueil --- drivers/memory/jz4780-nemc.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c index b232ed279fc3..647267ea8c63 100644 --- a/drivers/memory/jz4780-nemc.c +++ b/drivers/memory/jz4780-nemc.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -288,7 +289,19 @@ static int jz4780_nemc_probe(struct platform_device *pdev) nemc->dev = dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - nemc->base = devm_ioremap_resource(dev, res); + + /* + * The driver only uses the registers up to offset 0x54. Since the EFUSE + * registers are in the middle of the NEMC registers, we only request + * the registers we will use for now - that way the EFUSE driver can + * probe too. + */ + if (!devm_request_mem_region(dev, res->start, 0x54, dev_name(dev))) { + dev_err(dev, "unable to request I/O memory region\n"); + return -EBUSY; + } + + nemc->base = devm_ioremap(dev, res->start, resource_size(res)); if (IS_ERR(nemc->base)) { dev_err(dev, "failed to get I/O memory\n"); return PTR_ERR(nemc->base);