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[209.132.180.67]) by mx.google.com with ESMTP id cv19si9981249plb.165.2019.02.07.04.57.18; Thu, 07 Feb 2019 04:57:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cUcYK4rC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727392AbfBGM5R (ORCPT + 7 others); Thu, 7 Feb 2019 07:57:17 -0500 Received: from mail-pf1-f194.google.com ([209.85.210.194]:42257 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727389AbfBGM5Q (ORCPT ); Thu, 7 Feb 2019 07:57:16 -0500 Received: by mail-pf1-f194.google.com with SMTP id m6so1296292pfa.9 for ; Thu, 07 Feb 2019 04:57:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=weNMC1WOncVzrjA84l2O07eMcZ540Q8KJY50toWf3Z8=; b=cUcYK4rCNJFDiEGFjIMegVOFyeAXH42gm+HBUQUYfnP0NK+CEDN/WuiyjKGFlJTxkb L448RL2WEo3FdpcmRgEqXZ4vVw/T/88S2+LBLuYEmZJEVXo6rauTfiqt/+0Ei7uMYnYH 354o8YG0vPqGFfzrSOWm/zxBarnbn0Umv+9o2PUkcBjxZtItSkE1EllvCHpy6GS5Cn83 kmstKiUmEWFM8oOMH+OZI8ks9y1icZLmD6v8S4RKQmUCwtzW0JnsdCJqGkqGoWuGToUP aEi1rpDiV4zDwu0K+9+LFjW/nK5LeMhnzijHsZbbzoVGir1aNdyPQg0SbJOr7H8aJC4j NeUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=weNMC1WOncVzrjA84l2O07eMcZ540Q8KJY50toWf3Z8=; b=rjqmdePc0UBBVMBixhWX5mwVk+d6uwfJ0jness4VFg1tZA110l/jTVyrm9DG5ot45d Vph4Qo3w6pObd3PM6Mnw6oI/KCghirrrtl11XGLWdsL+/wP8DASF5Ft71W04barVfJJB niXhFwfZlJ8T3crRXPF8ZyIPv3K8+oWjgxC1b3Zc+zWTYM5a9EAbLE5Lv73qsFpXV/Pc 6QjTkYPns7JhsatA9vVYHMCmQnjd3H8E7JwHawmrPryjav0pFqXcSfk8PZQqDa4+FtDn bC/v7OFNI/jYbhL/5XvcXcTZaF5MQUHza8cnsXxuVEk8Kspqov9rSMOZwQ88X5ItFYZ0 Z3yA== X-Gm-Message-State: AHQUAuaYnNDquBiuAWxNiio3t20vrDOX9wwnnCHKZmTpfvvK/UMwLFlm yzmu0c8klVel56mhcXDoWJ4MGw== X-Received: by 2002:a62:4549:: with SMTP id s70mr15873687pfa.233.1549544236077; Thu, 07 Feb 2019 04:57:16 -0800 (PST) Received: from localhost ([2402:3a80:c80:4138:75dd:3900:1d90:762f]) by smtp.gmail.com with ESMTPSA id r6sm13488289pgk.91.2019.02.07.04.57.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 04:57:15 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v1 20/24] dt: thermal: tsens: Add bindings for qcs404 Date: Thu, 7 Feb 2019 16:19:38 +0530 Message-Id: <3f5a9282e815d2244b633a65e126494d23c16a7a.1549525708.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org qcs404 uses v1 of the TSENS IP block. Create a fallback DT property "qcom,tsens-v1" to gather common code Signed-off-by: Amit Kucheria --- .../devicetree/bindings/thermal/qcom-tsens.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt index 1d9e8cf61018..673cc1831ee9 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt @@ -6,11 +6,14 @@ Required properties: - "qcom,msm8916-tsens" (MSM8916) - "qcom,msm8974-tsens" (MSM8974) - "qcom,msm8996-tsens" (MSM8996) + - "qcom,qcs404-tsens", "qcom,tsens-v1" (QCS404) - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) The generic "qcom,tsens-v2" property must be used as a fallback for any SoC with version 2 of the TSENS IP. MSM8996 is the only exception because the generic property did not exist when support was added. + Similarly, the generic "qcom,tsens-v1" property must be used as a fallback for + any SoC with version 1 of the TSENS IP. - reg: Address range of the thermal registers. New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM @@ -39,3 +42,14 @@ tsens0: thermal-sensor@c263000 { #qcom,sensors = <13>; #thermal-sensor-cells = <1>; }; + +Example 3 (for any platform containing v1 of the TSENS IP): +tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + };