From patchwork Thu Nov 5 05:49:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 317957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B571DC388F9 for ; Thu, 5 Nov 2020 05:50:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 682E52087D for ; Thu, 5 Nov 2020 05:50:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726827AbgKEFuA (ORCPT ); Thu, 5 Nov 2020 00:50:00 -0500 Received: from mga01.intel.com ([192.55.52.88]:1217 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726626AbgKEFuA (ORCPT ); Thu, 5 Nov 2020 00:50:00 -0500 IronPort-SDR: uev50CdBgzIrOX8PFG79O5C+2+ippacr6PoXsSuapN1sm61k7mkTfsQmNDHuwtKkdNxSARSXGN X493IB511IEg== X-IronPort-AV: E=McAfee;i="6000,8403,9795"; a="187233773" X-IronPort-AV: E=Sophos;i="5.77,452,1596524400"; d="scan'208";a="187233773" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2020 21:49:55 -0800 IronPort-SDR: Lhpsas59DHDM5q+c7wbzCfCfoHs1MbAQIWSuFOxsDgmIU1gL6M1+gaZjM9zj8XRhX03bEuVDJi zKNPFDdCTpjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,452,1596524400"; d="scan'208";a="306385942" Received: from sgsxdev001.isng.intel.com (HELO localhost) ([10.226.88.11]) by fmsmga008.fm.intel.com with ESMTP; 04 Nov 2020 21:49:51 -0800 From: Rahul Tanwar To: u.kleine-koenig@pengutronix.de, linux-pwm@vger.kernel.org, lee.jones@linaro.org Cc: thierry.reding@gmail.com, p.zabel@pengutronix.de, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@intel.com, songjun.Wu@intel.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, rahul.tanwar.linux@gmail.com, Rahul Tanwar Subject: [PATCH v15 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC Date: Thu, 5 Nov 2020 13:49:39 +0800 Message-Id: <335475f02291b33aa4817d786a9b28a6fb206fd3.1604555266.git.rahul.tanwar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller which is only used to control the fan attached to the system. This PWM controller does not have any other consumer other than fan. Add DT bindings documentation for this PWM fan controller. Signed-off-by: Rahul Tanwar Reviewed-by: Rob Herring --- .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml new file mode 100644 index 000000000000..11a606536169 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LGM SoC PWM fan controller + +maintainers: + - Rahul Tanwar + +properties: + compatible: + const: intel,lgm-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + pwm: pwm@e0d00000 { + compatible = "intel,lgm-pwm"; + reg = <0xe0d00000 0x30>; + #pwm-cells = <2>; + clocks = <&cgu0 126>; + resets = <&rcu0 0x30 21>; + };