From patchwork Thu Jul 8 15:50:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 471450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_NONE, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C90C11F69 for ; Thu, 8 Jul 2021 15:50:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F12D36192A for ; Thu, 8 Jul 2021 15:50:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232107AbhGHPxH (ORCPT ); Thu, 8 Jul 2021 11:53:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:59362 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231945AbhGHPxF (ORCPT ); Thu, 8 Jul 2021 11:53:05 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 99971616EA; Thu, 8 Jul 2021 15:50:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625759423; bh=uCwa8ScPFO0U2r/s3wua3LONDVtbY/hwWP8xPNq4Iw4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QkAceOckiRR6IJtjS3hcBguwcAMkbGO+QQ46rN95bMUXVvPG3wtECROAM0q1CNJX8 BQ9urF579EYmxkHJj0T5ozj8v51kCtFWUI0BJqwMlttanq4gdoyPZt05JkLrIGCOBQ MvN66bNxthL6I76HwPZJETb0i3gvwXCNDY8yMqi3Ha1Ka6xKGRIu9ud7fxbrbp7QnP JPULNG6V2G65oUc8z2n1B5WuCszlhh8C/K2MGFWtGEK4aBQncMiEocm9LPol2PrDrV 8LKFTOu6KFNVbZ6lkkJIQ8epvrGqRpg6OFkYhnEHzFac6xTmlic0S99dQTGDQXP7KY aUsQy5w1QtxEQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m1WI4-008VVF-Iy; Thu, 08 Jul 2021 17:50:16 +0200 From: Mauro Carvalho Chehab To: Manivannan Sadhasivam , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Rob Herring , Vinod Koul , Wei Xu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH RFC 5/7] bindings: phy: add bindings for Hikey 960 PCIe PHY Date: Thu, 8 Jul 2021 17:50:12 +0200 Message-Id: <28b9aa4d2d182d4705d7837c9165ae7b5bd8d141.1625758732.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings for Hikey 960 (hi3660) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3660-pcie.yaml | 70 +++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +-- 2 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml new file mode 100644 index 000000000000..e91a38450461 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3660-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kirin960 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 960. + +properties: + compatible: + const: hisilicon,hi960-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe APB PHY clock + + clock-names: + items: + - const: pcie_phy_ref + - const: pcie_apb_phy + + reset-gpios: + description: PCI PERST reset GPIO(s) + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset-gpios + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>; + clock-names = "pcie_phy_ref", "pcie_apb_phy"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + }; +... diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3a589fa4ca81..96c978db12dc 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1006,8 +1006,10 @@ pcie_phy: pcie-phy@f3f2000 { reg = <0x0 0xf3f20000 0x0 0x40000>; reg-names = "phy"; clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>; - clock-names = "pcie_phy_ref", "pcie_apb_phy"; + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_apb_phy", + "pcie_aclk"; reset-gpios = <&gpio11 1 0 >; #phy-cells = <0>; }; @@ -1040,9 +1042,8 @@ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_aux", "pcie_apb_sys", "pcie_aclk"; + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>; + clock-names = "pcie_aux", "pcie_apb_sys"; }; /* UFS */