| Message ID | 223a1d8020d50c35ff2621f95d69b4a626b6893b.1626986805.git.quic_vamslank@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
On 7/23/2021 2:39 AM, quic_vamslank@quicinc.com wrote: > From: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > > Add a new PLL type for SDX65 SoC from Qualcomm. > > Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > --- > drivers/clk/qcom/clk-alpha-pll.c | 170 +++++++++++++++++++++++++++++++ > drivers/clk/qcom/clk-alpha-pll.h | 4 + > 2 files changed, 174 insertions(+) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index c6eb99169ddc..93c8917b7273 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -1,5 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. > * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. > */ > > @@ -126,6 +127,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { > [PLL_OFF_TEST_CTL_U] = 0x1c, > [PLL_OFF_STATUS] = 0x2c, > }, > + [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { > + [PLL_OFF_OPMODE] = 0x04, > + [PLL_OFF_STATUS] = 0x0c, > + [PLL_OFF_L_VAL] = 0x10, > + [PLL_OFF_ALPHA_VAL] = 0x14, > + [PLL_OFF_USER_CTL] = 0x18, > + [PLL_OFF_USER_CTL_U] = 0x1c, > + [PLL_OFF_CONFIG_CTL] = 0x20, > + [PLL_OFF_CONFIG_CTL_U] = 0x24, > + [PLL_OFF_CONFIG_CTL_U1] = 0x28, > + [PLL_OFF_TEST_CTL] = 0x2c, > + [PLL_OFF_TEST_CTL_U] = 0x30, > + [PLL_OFF_TEST_CTL_U1] = 0x34, > + }, > }; > EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > > @@ -155,12 +170,14 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > > /* LUCID PLL specific settings and offsets */ > #define LUCID_PCAL_DONE BIT(27) > +#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) > > /* LUCID 5LPE PLL specific settings and offsets */ > #define LUCID_5LPE_PCAL_DONE BIT(11) > #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) > #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) > #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) Please add a comment /* LUCID EVO PLL specific settings and offsets */ > +#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) > > #define pll_alpha_width(p) \ > ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ > @@ -1777,3 +1794,156 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { > .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, > }; > EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); > + > +static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + u32 val; > + int ret; > + > + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return ret; > + > + /* If in FSM mode, just vote for it */ > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { > + ret = clk_enable_regmap(hw); > + if (ret) > + return ret; > + return wait_for_pll_enable_lock(pll); > + } > + > + /* Check if PLL is already enabled */ > + ret = trion_pll_is_enabled(pll, pll->clkr.regmap); > + if (ret < 0) > + return ret; > + else if (ret) { > + pr_warn("%s PLL is already enabled\n", > + clk_hw_get_name(&pll->clkr.hw)); > + return 0; > + } > + > + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), > + PLL_RESET_N, PLL_RESET_N); > + if (ret) > + return ret; > + > + /* Set operation mode to RUN */ > + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); > + > + ret = wait_for_pll_enable_lock(pll); > + if (ret) > + return ret; > + > + /* Enable the PLL outputs */ > + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), > + PLL_OUT_MASK, PLL_OUT_MASK); > + if (ret) > + return ret; > + > + /* Enable the global PLL outputs */ > + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), > + PLL_OUTCTRL, PLL_OUTCTRL); > + if (ret) > + return ret; > + > + /* Ensure that the write above goes through before returning. */ > + mb(); > + return ret; > +} > + > +static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + u32 val; > + int ret; > + > + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return; > + > + /* If in FSM mode, just unvote it */ > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { > + clk_disable_regmap(hw); > + return; > + } > + > + /* Disable the global PLL output */ > + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), > + PLL_OUTCTRL, 0); > + if (ret) > + return; > + > + /* Disable the PLL outputs */ > + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), > + PLL_OUT_MASK, 0); > + if (ret) > + return; > + > + /* Place the PLL mode in STANDBY */ > + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), > + PLL_STANDBY); > +} > + > +static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + u32 l, frac; > + > + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); > + l &= LUCID_EVO_PLL_L_VAL_MASK; > + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); > + > + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_REG_16BIT_WIDTH); Can you please use "pll_alpha_width(pll)". > +} > + > +static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, > + unsigned long rate, unsigned long parent_rate) > +{ > + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); > + int i, val = 0, div, ret; 'val' not required to be initialized. > + > + /* > + * If the PLL is in FSM mode, then treat set_rate callback as a > + * no-operation. > + */ > + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return ret; > + > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) > + return 0; > + > + if (!pll->post_div_table) { > + pr_err("Missing the post_div_table for the PLL\n"); > + return -EINVAL; > + } > + > + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); > + for (i = 0; i < pll->num_post_div; i++) { > + if (pll->post_div_table[i].div == div) { > + val = pll->post_div_table[i].val; > + break; > + } > + } > + > + return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), > + (BIT(pll->width) - 1) << pll->post_div_shift, > + val << pll->post_div_shift); > +} > + > +const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { > + .enable = alpha_pll_lucid_evo_enable, > + .disable = alpha_pll_lucid_evo_disable, > + .is_enabled = clk_trion_pll_is_enabled, > + .recalc_rate = alpha_pll_lucid_evo_recalc_rate, > + .round_rate = clk_alpha_pll_round_rate, > +}; > +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); > + > +const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { > + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, > + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, > + .set_rate = clk_lucid_evo_pll_postdiv_set_rate, > +}; > +EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h > index 6943e933be0f..c42299bf6f6f 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.h > +++ b/drivers/clk/qcom/clk-alpha-pll.h > @@ -16,6 +16,7 @@ enum { > CLK_ALPHA_PLL_TYPE_TRION, > CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, > CLK_ALPHA_PLL_TYPE_AGERA, > + CLK_ALPHA_PLL_TYPE_LUCID_EVO, > CLK_ALPHA_PLL_TYPE_MAX, > }; > > @@ -148,6 +149,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; > extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; > extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; > > +extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; > +extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; > + > void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > const struct alpha_pll_config *config); > void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Hello Vamsi, On 22-07-21, 14:09, quic_vamslank@quicinc.com wrote: > From: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Can you please add the type of pll in patch title. Something like Add LUCID_EVO pll > > Add a new PLL type for SDX65 SoC from Qualcomm. > > Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > --- > drivers/clk/qcom/clk-alpha-pll.c | 170 +++++++++++++++++++++++++++++++ > drivers/clk/qcom/clk-alpha-pll.h | 4 + > 2 files changed, 174 insertions(+) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index c6eb99169ddc..93c8917b7273 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -1,5 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. > * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. > */ > > @@ -126,6 +127,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { > [PLL_OFF_TEST_CTL_U] = 0x1c, > [PLL_OFF_STATUS] = 0x2c, > }, > + [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { > + [PLL_OFF_OPMODE] = 0x04, > + [PLL_OFF_STATUS] = 0x0c, > + [PLL_OFF_L_VAL] = 0x10, > + [PLL_OFF_ALPHA_VAL] = 0x14, > + [PLL_OFF_USER_CTL] = 0x18, > + [PLL_OFF_USER_CTL_U] = 0x1c, > + [PLL_OFF_CONFIG_CTL] = 0x20, > + [PLL_OFF_CONFIG_CTL_U] = 0x24, > + [PLL_OFF_CONFIG_CTL_U1] = 0x28, > + [PLL_OFF_TEST_CTL] = 0x2c, > + [PLL_OFF_TEST_CTL_U] = 0x30, > + [PLL_OFF_TEST_CTL_U1] = 0x34, > + }, > }; > EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > > @@ -155,12 +170,14 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); > > /* LUCID PLL specific settings and offsets */ > #define LUCID_PCAL_DONE BIT(27) > +#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) > > /* LUCID 5LPE PLL specific settings and offsets */ > #define LUCID_5LPE_PCAL_DONE BIT(11) > #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) > #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) > #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) > +#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) > > #define pll_alpha_width(p) \ > ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ > @@ -1777,3 +1794,156 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { > .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, > }; > EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); > + > +static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); Use a regmap ptr like we do for other functions here? > + u32 val; > + int ret; > + > + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return ret; > + > + /* If in FSM mode, just vote for it */ > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { > + ret = clk_enable_regmap(hw); > + if (ret) > + return ret; > + return wait_for_pll_enable_lock(pll); > + } > + > + /* Check if PLL is already enabled */ > + ret = trion_pll_is_enabled(pll, pll->clkr.regmap); > + if (ret < 0) > + return ret; > + else if (ret) { > + pr_warn("%s PLL is already enabled\n", > + clk_hw_get_name(&pll->clkr.hw)); > + return 0; > + } > + > + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), > + PLL_RESET_N, PLL_RESET_N); this and others should fit in a single line (with regmap ptr) > + if (ret) > + return ret; > + > + /* Set operation mode to RUN */ > + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); > + > + ret = wait_for_pll_enable_lock(pll); > + if (ret) > + return ret; > + > + /* Enable the PLL outputs */ > + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), > + PLL_OUT_MASK, PLL_OUT_MASK); > + if (ret) > + return ret; > + > + /* Enable the global PLL outputs */ > + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), > + PLL_OUTCTRL, PLL_OUTCTRL); > + if (ret) > + return ret; > + > + /* Ensure that the write above goes through before returning. */ > + mb(); why is this required? > + return ret; > +} > + > +static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); regmap here too > + u32 val; > + int ret; > + > + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return; > + > + /* If in FSM mode, just unvote it */ > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { > + clk_disable_regmap(hw); > + return; > + } > + > + /* Disable the global PLL output */ > + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), > + PLL_OUTCTRL, 0); > + if (ret) > + return; > + > + /* Disable the PLL outputs */ > + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), > + PLL_OUT_MASK, 0); > + if (ret) > + return; > + > + /* Place the PLL mode in STANDBY */ > + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), > + PLL_STANDBY); > +} > + > +static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) too long pls split to two lines! > +{ > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + u32 l, frac; > + > + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); > + l &= LUCID_EVO_PLL_L_VAL_MASK; > + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); > + > + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_REG_16BIT_WIDTH); > +} looks like you should reuse clk_trion_pll_recalc_rate() instead... > + > +static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, > + unsigned long rate, unsigned long parent_rate) > +{ > + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); > + int i, val = 0, div, ret; > + > + /* > + * If the PLL is in FSM mode, then treat set_rate callback as a > + * no-operation. > + */ > + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); > + if (ret) > + return ret; > + > + if (val & LUCID_EVO_ENABLE_VOTE_RUN) > + return 0; > + > + if (!pll->post_div_table) { > + pr_err("Missing the post_div_table for the PLL\n"); > + return -EINVAL; > + } > + > + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); > + for (i = 0; i < pll->num_post_div; i++) { > + if (pll->post_div_table[i].div == div) { > + val = pll->post_div_table[i].val; > + break; > + } > + } > + > + return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), > + (BIT(pll->width) - 1) << pll->post_div_shift, > + val << pll->post_div_shift); > +} clk_lucid_5lpe_pll_postdiv_set_rate() looks similar? -- ~Vinod
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index c6eb99169ddc..93c8917b7273 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ @@ -126,6 +127,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x1c, [PLL_OFF_STATUS] = 0x2c, }, + [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { + [PLL_OFF_OPMODE] = 0x04, + [PLL_OFF_STATUS] = 0x0c, + [PLL_OFF_L_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL] = 0x14, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0x1c, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_CONFIG_CTL_U1] = 0x28, + [PLL_OFF_TEST_CTL] = 0x2c, + [PLL_OFF_TEST_CTL_U] = 0x30, + [PLL_OFF_TEST_CTL_U1] = 0x34, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -155,12 +170,14 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); /* LUCID PLL specific settings and offsets */ #define LUCID_PCAL_DONE BIT(27) +#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) /* LUCID 5LPE PLL specific settings and offsets */ #define LUCID_5LPE_PCAL_DONE BIT(11) #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) +#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) #define pll_alpha_width(p) \ ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ @@ -1777,3 +1794,156 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, }; EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); + +static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; + int ret; + + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return ret; + + /* If in FSM mode, just vote for it */ + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { + ret = clk_enable_regmap(hw); + if (ret) + return ret; + return wait_for_pll_enable_lock(pll); + } + + /* Check if PLL is already enabled */ + ret = trion_pll_is_enabled(pll, pll->clkr.regmap); + if (ret < 0) + return ret; + else if (ret) { + pr_warn("%s PLL is already enabled\n", + clk_hw_get_name(&pll->clkr.hw)); + return 0; + } + + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), + PLL_RESET_N, PLL_RESET_N); + if (ret) + return ret; + + /* Set operation mode to RUN */ + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); + + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + /* Enable the PLL outputs */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_OUT_MASK, PLL_OUT_MASK); + if (ret) + return ret; + + /* Enable the global PLL outputs */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), + PLL_OUTCTRL, PLL_OUTCTRL); + if (ret) + return ret; + + /* Ensure that the write above goes through before returning. */ + mb(); + return ret; +} + +static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; + int ret; + + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return; + + /* If in FSM mode, just unvote it */ + if (val & LUCID_EVO_ENABLE_VOTE_RUN) { + clk_disable_regmap(hw); + return; + } + + /* Disable the global PLL output */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), + PLL_OUTCTRL, 0); + if (ret) + return; + + /* Disable the PLL outputs */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_OUT_MASK, 0); + if (ret) + return; + + /* Place the PLL mode in STANDBY */ + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), + PLL_STANDBY); +} + +static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l, frac; + + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + l &= LUCID_EVO_PLL_L_VAL_MASK; + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); + + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_REG_16BIT_WIDTH); +} + +static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + int i, val = 0, div, ret; + + /* + * If the PLL is in FSM mode, then treat set_rate callback as a + * no-operation. + */ + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return ret; + + if (val & LUCID_EVO_ENABLE_VOTE_RUN) + return 0; + + if (!pll->post_div_table) { + pr_err("Missing the post_div_table for the PLL\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + for (i = 0; i < pll->num_post_div; i++) { + if (pll->post_div_table[i].div == div) { + val = pll->post_div_table[i].val; + break; + } + } + + return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + (BIT(pll->width) - 1) << pll->post_div_shift, + val << pll->post_div_shift); +} + +const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { + .enable = alpha_pll_lucid_evo_enable, + .disable = alpha_pll_lucid_evo_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = alpha_pll_lucid_evo_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); + +const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, + .set_rate = clk_lucid_evo_pll_postdiv_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6943e933be0f..c42299bf6f6f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -16,6 +16,7 @@ enum { CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_AGERA, + CLK_ALPHA_PLL_TYPE_LUCID_EVO, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -148,6 +149,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; +extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; +extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,