From patchwork Sat Feb 3 02:36:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 769639 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DE9D1BF3D; Sat, 3 Feb 2024 02:37:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706927878; cv=none; b=q2jfK78cQc9VXxdsaFjzEjLo7BqLOiHznnlrp2WYn2ehUYTqIFphbLKhQPnoK7Qf5wOjmjaGmIicB70fW+jEkdpoEZ2UTrhp/1MLV9kJZSEcOXHXCeLeKIUUNR5Sgt16U0WfkXBgbWJmwuTcuG7yNbKdBlgfYpVLaBrV5gBdXMA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706927878; c=relaxed/simple; bh=CtxumE9xy8E75NV5EAWv+2S2i06ql2rIZ/FBzOnULFc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fQU6Ghg7lo09SbtJszm0TYYuI18DzDC3z96esn8S5NctSQcOW8+HVJhig+2RRTjKZDXyFJlgV0TzvjvdkeC1SKgIYi15ovQ6sdlWVYPKpPdQG0bYumtQaMEROB1tXk1pcYpZReqUZGWLkjGfngIvhGPWS6vD/6yfTd0YaH7HWeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=oALaQOPI; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="oALaQOPI" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4132bROX029984; Sat, 3 Feb 2024 02:37:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=LylXK/jrWURWDhUw7tH5 hZ4ow+Xl5FX/mchvOMoIBg8=; b=oALaQOPIz4LutQyOM4mN+1dUUADFez1M4i/i YDtlVyUp5ZORExXHo/IC1+9ShJW3CvykVyzQag9JJZRjJSAxjP4/u2qBuAF7I8Y8 wufHqFFl8R4wh98sWPoOGqojdksAuIbRoEzdsx/ZRWu46oG0Li1liu/Sij1+P8gI 0nyZojfCl4YV8ngtOVp0Z6qo50IsSwLhBLvtDGO84QTEksNXcjoZDVT6LxRlthWf CwVxrESsU9pIqkZmmz9McM3TLJTHKQESbO2mNgHTv1+FO4Ac1S7UAOgCS1JKkxy2 45N/1wiAcz1fyqb+B//bzWO7rHgLPlDvVsM9tceqYBfjjR8fiw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w0ptwawr9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 03 Feb 2024 02:37:27 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4132bLN1003539 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 3 Feb 2024 02:37:22 GMT Received: from hu-wcheng-lv.qualcomm.com (10.49.16.6) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 2 Feb 2024 18:37:21 -0800 From: Wesley Cheng To: , , , , , , , , , , , , , , CC: , , , , , , , Wesley Cheng Subject: [PATCH v13 15/53] xhci: export XHCI IMOD setting helper for interrupters Date: Fri, 2 Feb 2024 18:36:07 -0800 Message-ID: <20240203023645.31105-16-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203023645.31105-1-quic_wcheng@quicinc.com> References: <20240203023645.31105-1-quic_wcheng@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Tge1x0AI4-K1mpTlnoucUGzq7T_9x34u X-Proofpoint-GUID: Tge1x0AI4-K1mpTlnoucUGzq7T_9x34u X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-02_16,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 mlxlogscore=638 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402030015 Utilize the xhci_set_interrupter_moderation() API to set the IMOD value for interrupters, so that secondary interrupts can also configure this parameter when clients request for it. Signed-off-by: Wesley Cheng --- drivers/usb/host/xhci.c | 3 ++- drivers/usb/host/xhci.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 834d8d160da4..d2ce1e1421e6 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -349,7 +349,7 @@ int xhci_disable_interrupter(struct xhci_interrupter *ir) EXPORT_SYMBOL_GPL(xhci_disable_interrupter); /* interrupt moderation interval imod_interval in nanoseconds */ -static int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, +int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, u32 imod_interval) { u32 imod; @@ -364,6 +364,7 @@ static int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, return 0; } +EXPORT_SYMBOL_GPL(xhci_set_interrupter_moderation); static void compliance_mode_recovery(struct timer_list *t) { diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index ad9d93c645ad..d88d2f67e3ed 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1874,6 +1874,8 @@ int xhci_alloc_tt_info(struct xhci_hcd *xhci, struct usb_tt *tt, gfp_t mem_flags); int xhci_enable_interrupter(struct xhci_interrupter *ir); int xhci_disable_interrupter(struct xhci_interrupter *ir); +int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, + u32 imod_interval); /* xHCI ring, segment, TRB, and TD functions */ dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);