From patchwork Mon Jan 29 09:25:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 767731 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B50C58ABA; Mon, 29 Jan 2024 09:28:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706520497; cv=none; b=VIQteZGfk1R4c7VY1ZMd+/dZqXQWsR0hkAelZpLMYlVcyxW20FcOumnP+HlzDKNBrSy3SMwMIEO9Pm9tityZcAlnDKNt3id/EiTHj6mZ8RMT/nY1RXPp4/oYpmapsrtEhlRHo4tiVAxK48ABpIunhoACr1egi1bVyLvJ7Lpmo2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706520497; c=relaxed/simple; bh=ZpsePdhkqsFzOwuoHVhBYBar6q2hFDLcTLjSFVdzv7w=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tkXxqVgFIJS27MVDdnHyiDhdkRDgDnRkdbaCZA8yiqGMSDrSOZbl2GCzvJkatp7ZbzMEGyf3yew5Ig2yejcJ7uvHTxE6p9yk5qNt5N5xll5LVe1/Nu17FDzCqsTwYAGjV6G8Nc4wtulmPW132BRp2pTykyEdEbjJz2+mTCZMXR8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 40T9QJ1g080108; Mon, 29 Jan 2024 17:26:20 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 29 Jan 2024 17:26:17 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Date: Mon, 29 Jan 2024 17:25:47 +0800 Message-ID: <20240129092553.2058043-5-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129092553.2058043-1-peterlin@andestech.com> References: <20240129092553.2058043-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 40T9QJ1g080108 Add "andestech,cpu-intc" compatible string to indicate that Andes specific local interrupt is supported on the core, e.g. AX45MP cores have 3 types of non-standard local interrupt which can be handled in supervisor mode: - Slave port ECC error interrupt - Bus write transaction error interrupt - Performance monitor overflow interrupt These interrupts are enabled/disabled via a custom register SLIE instead of the standard interrupt enable register SIE. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Updated commit message - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - Add const entry instead of enum (Suggested by Conor) Changes v4 -> v5: - Include Conor's Acked-by - Include Prabhakar's Reviewed-by Changes v5 -> v6: - No change Changes v6 -> v7: - No change Changes v7 -> v8: - No change --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 9d8670c00e3b..6ccd75cbbc59 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -106,7 +106,11 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - const: andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true