From patchwork Fri Jan 26 18:18:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 766595 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DA6E20DE6; Fri, 26 Jan 2024 18:29:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706293769; cv=none; b=QrJo7bQCH77qwoeE0K0R4Jz8JeROr9rhjVHSw0j4KHH+xUtEMOC+P/PNq582TCirkUSkFETGaNFFhTimGfzsKQ3RfDCL6r4wPGJOjaJ8F1EuvnBJNGI32fOyPm+pimH/ueSpEDz7yRQVpUnwVebnhPRE38yVbW0O3NVlTvReON0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706293769; c=relaxed/simple; bh=krD6cO2tyhVXcVkpXWJFsU7KStdBrYWbgIJ6Se6IRkI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GlrmEKEHvUILkw75oYoTpqbMGh4Ktdrjwr5TIEcFNauypEtyRqX64GnOoyh8htDoYH/X028P1cR9PdtAsIJqKVSC25cuoqQ5r0Ff/jG5kNU6jOo3Lt1bHt2lz8lXzCkp0k59eswrGpdyPLkR8jItnOIxNNNOOLAuQSIvxin3CSk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=RTjQ9+ov; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="RTjQ9+ov" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1706293762; bh=krD6cO2tyhVXcVkpXWJFsU7KStdBrYWbgIJ6Se6IRkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RTjQ9+ov2t51CO7+6IwuV+Htp17mBwPpGHtUspEFva0YXHMsQTS+LFARL3kD49jJC gO6s98UrHAxeq4gLvA5+Dh1DXKtI+8Y5AaNA+a2XR7r+pzYfHyQjk/lv8PilTN66CS wcD7KWoJN1z+WbMEzT10jUPI5wxNiqKy0aur4GTR7fS2zo7iyJS2XXSkca7iJ1GIP2 V9R7bxCHtlFLDUgd63OcJ1cnohX9PJ8PafZjUBt9UWszwGFDQ+V6rNuPpDhF5syIXK oeIPuLeXUOVr2u+yEQRYePAtq2U0AuMCJH4WhZyYbpsPn2hHBirgUbexMzj3WH61vl lcq4UQyb1iyRQ== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 89FC93782089; Fri, 26 Jan 2024 18:29:22 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 9F434482ACC; Fri, 26 Jan 2024 19:29:21 +0100 (CET) From: Sebastian Reichel To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Cc: Elaine Zhang , Kever Yang , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , huangtao@rock-chips.com, andy.yan@rock-chips.com, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v8 7/7] clk: rockchip: implement proper GATE_LINK support Date: Fri, 26 Jan 2024 19:18:28 +0100 Message-ID: <20240126182919.48402-8-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240126182919.48402-1-sebastian.reichel@collabora.com> References: <20240126182919.48402-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These effectively need two parent clocks. GATE_LINK type clocks handle the second parent via 'linkedclk' by using runtime PM clocks. To make that possible a new platform device is created for every clock handled in this way. Note, that before this patch clk_rk3588_probe() has never been called, because CLK_OF_DECLARE marks the DT node as processed. This patch replaces that with CLK_OF_DECLARE_DRIVER and thus the probe function is used now. This is necessary to have 'struct device' available. Also instead of builtin_platform_driver_probe, the driver has been switched to use core_initcall, since it should be fully probed before the Rockchip PM domain driver (and that is using postcore_initcall). Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk-rk3588.c | 122 +++++++++++++----------------- drivers/clk/rockchip/clk.c | 69 ++++++++++++++++- drivers/clk/rockchip/clk.h | 16 ++++ 3 files changed, 138 insertions(+), 69 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index b30279a96dc8..f0eb380b727c 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -12,28 +12,6 @@ #include #include "clk.h" -/* - * Recent Rockchip SoCs have a new hardware block called Native Interface - * Unit (NIU), which gates clocks to devices behind them. These effectively - * need two parent clocks. - * - * Downstream enables the linked clock via runtime PM whenever the gate is - * enabled. This implementation uses separate clock nodes for each of the - * linked gate clocks, which leaks parts of the clock tree into DT. - * - * The GATE_LINK macro instead takes the second parent via 'linkname', but - * ignores the information. Once the clock framework is ready to handle it, the - * information should be passed on here. But since these clocks are required to - * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked - * clocks critical until a better solution is available. This will waste some - * power, but avoids leaking implementation details into DT or hanging the - * system. - */ -#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ - GATE(_id, cname, pname, f, o, b, gf) -#define RK3588_LINKED_CLK CLK_IS_CRITICAL - - #define RK3588_GRF_SOC_STATUS0 0x600 #define RK3588_PHYREF_ALT_GATE 0xc38 @@ -266,6 +244,8 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { }, \ } +static struct rockchip_clk_provider *early_ctx; + static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { RK3588_CPUB01CLK_RATE(2496000000, 1), RK3588_CPUB01CLK_RATE(2400000000, 1), @@ -694,7 +674,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), }; -static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { +static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { /* * CRU Clock-Architecture */ @@ -1456,7 +1436,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, RK3588_CLKGATE_CON(31), 0, GFLAGS), - COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(31), 1, GFLAGS), GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, @@ -1685,13 +1665,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(42), 9, GFLAGS), /* vdpu */ - COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(44), 0, GFLAGS), COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, RK3588_CLKGATE_CON(44), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, RK3588_CLKGATE_CON(44), 2, GFLAGS), COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, @@ -1742,9 +1722,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(47), 1, GFLAGS), - GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, + GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, RK3588_CLKGATE_CON(47), 4, GFLAGS), - GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, + GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, RK3588_CLKGATE_CON(47), 5, GFLAGS), COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, @@ -1754,10 +1734,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(48), 6, GFLAGS), /* vi */ - COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(49), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, RK3588_CLKGATE_CON(49), 1, GFLAGS), COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, @@ -1927,10 +1907,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(52), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, RK3588_CLKGATE_CON(52), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, RK3588_CLKGATE_CON(52), 2, GFLAGS), COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, @@ -2428,10 +2408,12 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(68), 5, GFLAGS), GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, RK3588_CLKGATE_CON(68), 2, GFLAGS), +}; +static struct rockchip_clk_branch rk3588_clk_branches[] = { GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), - GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), + GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), @@ -2443,9 +2425,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), - GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), - GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), @@ -2453,14 +2435,18 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), }; -static void __init rk3588_clk_init(struct device_node *np) +static void __init rk3588_clk_early_init(struct device_node *np) { struct rockchip_clk_provider *ctx; - unsigned long clk_nr_clks; + unsigned long clk_nr_clks, max_clk_id1, max_clk_id2; void __iomem *reg_base; - clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches, - ARRAY_SIZE(rk3588_clk_branches)) + 1; + max_clk_id1 = rockchip_clk_find_max_clk_id(rk3588_clk_branches, + ARRAY_SIZE(rk3588_clk_branches)); + max_clk_id2 = rockchip_clk_find_max_clk_id(rk3588_early_clk_branches, + ARRAY_SIZE(rk3588_early_clk_branches)); + clk_nr_clks = max(max_clk_id1, max_clk_id2) + 1; + reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: could not map cru region\n", __func__); @@ -2473,6 +2459,7 @@ static void __init rk3588_clk_init(struct device_node *np) iounmap(reg_base); return; } + early_ctx = ctx; rockchip_clk_register_plls(ctx, rk3588_pll_clks, ARRAY_SIZE(rk3588_pll_clks), @@ -2491,54 +2478,53 @@ static void __init rk3588_clk_init(struct device_node *np) &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, ARRAY_SIZE(rk3588_cpub1clk_rates)); + rockchip_clk_register_branches(ctx, rk3588_early_clk_branches, + ARRAY_SIZE(rk3588_early_clk_branches)); + + rockchip_clk_of_add_provider(np, ctx); +} +CLK_OF_DECLARE_DRIVER(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_early_init); + +static int clk_rk3588_probe(struct platform_device *pdev) +{ + struct rockchip_clk_provider *ctx = early_ctx; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + rockchip_clk_register_branches(ctx, rk3588_clk_branches, ARRAY_SIZE(rk3588_clk_branches)); - rk3588_rst_init(np, reg_base); - + rk3588_rst_init(np, ctx->reg_base); rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); + /* + * Re-add clock provider, so that the newly added clocks are also + * re-parented and get their defaults configured. + */ + of_clk_del_provider(np); rockchip_clk_of_add_provider(np, ctx); -} -CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); - -struct clk_rk3588_inits { - void (*inits)(struct device_node *np); -}; - -static const struct clk_rk3588_inits clk_3588_cru_init = { - .inits = rk3588_clk_init, -}; + return 0; +} static const struct of_device_id clk_rk3588_match_table[] = { { .compatible = "rockchip,rk3588-cru", - .data = &clk_3588_cru_init, }, { } }; -static int __init clk_rk3588_probe(struct platform_device *pdev) -{ - const struct clk_rk3588_inits *init_data; - struct device *dev = &pdev->dev; - - init_data = device_get_match_data(dev); - if (!init_data) - return -EINVAL; - - if (init_data->inits) - init_data->inits(dev->of_node); - - return 0; -} - static struct platform_driver clk_rk3588_driver = { + .probe = clk_rk3588_probe, .driver = { .name = "clk-rk3588", .of_match_table = clk_rk3588_match_table, .suppress_bind_attrs = true, }, }; -builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe); + +static int __init rockchip_clk_rk3588_drv_register(void) +{ + return platform_driver_register(&clk_rk3588_driver); +} +core_initcall(rockchip_clk_rk3588_drv_register); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 73d2cbdc716b..5807f1d820d6 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -19,8 +19,12 @@ #include #include #include +#include +#include +#include #include #include +#include #include "../clk-fractional-divider.h" #include "clk.h" @@ -376,7 +380,7 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, goto err_free; for (i = 0; i < nr_clks; ++i) - clk_table[i] = ERR_PTR(-ENOENT); + clk_table[i] = ERR_PTR(-EPROBE_DEFER); ctx->reg_base = base; ctx->clk_data.clks = clk_table; @@ -446,6 +450,66 @@ unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, } EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id); +static struct platform_device *rockchip_clk_register_pdev( + struct platform_device *parent, + const char *name, + struct device_node *np) +{ + struct platform_device_info pdevinfo = { + .parent = &parent->dev, + .name = name, + .fwnode = of_fwnode_handle(np), + .of_node_reused = true, + }; + + return platform_device_register_full(&pdevinfo); +} + +static struct clk *rockchip_clk_register_linked_gate( + struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *clkbr) +{ + struct clk *linked_clk = ctx->clk_data.clks[clkbr->linked_clk_id]; + unsigned long flags = clkbr->flags | CLK_SET_RATE_PARENT; + struct device_node *np = ctx->cru_node; + struct platform_device *parent, *pdev; + struct device *dev = NULL; + int ret; + + parent = of_find_device_by_node(np); + if (!parent) { + pr_err("failed to find device for %pOF\n", np); + goto exit; + } + + pdev = rockchip_clk_register_pdev(parent, clkbr->name, np); + put_device(&parent->dev); + if (!pdev) { + pr_err("failed to register device for clock %s\n", clkbr->name); + goto exit; + } + + dev = &pdev->dev; + pm_runtime_enable(dev); + ret = pm_clk_create(dev); + if (ret) { + pr_err("failed to create PM clock list for %s\n", clkbr->name); + goto exit; + } + + ret = pm_clk_add_clk(dev, linked_clk); + if (ret) { + pr_err("failed to setup linked clock for %s\n", clkbr->name); + } + +exit: + return clk_register_gate(dev, clkbr->name, + clkbr->parent_names[0], flags, + ctx->reg_base + clkbr->gate_offset, + clkbr->gate_shift, clkbr->gate_flags, + &ctx->lock); +} + void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, struct rockchip_clk_branch *list, unsigned int nr_clk) @@ -526,6 +590,9 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, ctx->reg_base + list->gate_offset, list->gate_shift, list->gate_flags, &ctx->lock); break; + case branch_linked_gate: + clk = rockchip_clk_register_linked_gate(ctx, list); + break; case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index fd3b476dedda..0d8e729fe332 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -517,6 +517,7 @@ enum rockchip_clk_branch_type { branch_divider, branch_fraction_divider, branch_gate, + branch_linked_gate, branch_mmc, branch_inverter, branch_factor, @@ -544,6 +545,7 @@ struct rockchip_clk_branch { int gate_offset; u8 gate_shift; u8 gate_flags; + unsigned int linked_clk_id; struct rockchip_clk_branch *child; }; @@ -842,6 +844,20 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ + { \ + .id = _id, \ + .branch_type = branch_linked_gate, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .linked_clk_id = linkedclk, \ + .num_parents = 1, \ + .flags = f, \ + .gate_offset = o, \ + .gate_shift = b, \ + .gate_flags = gf, \ + } + #define MMC(_id, cname, pname, offset, shift) \ { \ .id = _id, \