From patchwork Thu Jan 25 09:31:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu via B4 Relay X-Patchwork-Id: 766158 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90A771C6B5; Thu, 25 Jan 2024 09:31:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706175081; cv=none; b=JUrPZKPnIN0BBnOgP+NIugGveTJ5zKDj3WmKj4GoRFVzP7Px3DKIz2hZT2Vl89EZ7ALnUTVY6ttG14vF1gBkXPzmIXMbYR+OTUEtu4C93Y5BDX2TZ72qZRi/FMJIN6GHd/F5FLAdBYgoYEY9QyDHSGe/Gq5U3Q4GtIUkjEagPRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706175081; c=relaxed/simple; bh=Ps10833wypwJ8dn+FUUD3YYZv9hJD8JaPef8VSJqtG4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZL9cRlJhYr0/AZ901wWhCElTNibUYXWK+40w69gkUeL1Kd+r9mXNPgdYWKTYzfe/ZTAI5h6DA1ihQWQ9nidQ7u9jUTQtsMA0EPYeSKBafvB3prhQGVR7EUFsqb8bBWLinbU/V/MDkznmn1gbe+Lv3VgnTsjSlCtTmf/O4SS2ma8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ouYSPqd9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ouYSPqd9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3AC07C43390; Thu, 25 Jan 2024 09:31:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1706175081; bh=Ps10833wypwJ8dn+FUUD3YYZv9hJD8JaPef8VSJqtG4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ouYSPqd99Exa2yXkHuT1POlETH5Vh0qC5XRAAiDUrWzRM/WxB1yEPhCHzDmChSKIj kLWI2i8baJiDW6rxxMJ/5GZzkiu0T8Z4goSG1AIa7A/jlnlITDIBsFSetQgrdApK0M MduAipWKq0wTRnFGgkSP4GkQe3Zw8kD7U0ijd5Cm+8vZOcnpAgIJi6yOlhpF2vPGxP k4lFXVrR5vKgyITRcmYRivlsyYOpGVM9KwewkXXzDiNkvnpXk7FVjBbmpmwwG1SVvB aPFx9s/mkkzpJoYldTs8V+Subh5sn/6ixrDWCU6HTx8aNzlv1xSGHi3KRBn63T5pNz 17aJP8wvGp1fg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16B1AC48285; Thu, 25 Jan 2024 09:31:21 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Thu, 25 Jan 2024 17:31:15 +0800 Subject: [PATCH v3 1/2] arm64: dts: qcom: sm8650-mtp: add PM8010 regulators Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240125-sm8650_pm8010_support-v3-1-2f291242a7c4@quicinc.com> References: <20240125-sm8650_pm8010_support-v3-0-2f291242a7c4@quicinc.com> In-Reply-To: <20240125-sm8650_pm8010_support-v3-0-2f291242a7c4@quicinc.com> To: kernel@quicinc.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_collinsd@quicinc.com, Fenglin Wu X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706175079; l=4668; i=quic_fenglinw@quicinc.com; s=20230725; h=from:subject:message-id; bh=c1WJiXPJ0FmZO+G5zACGQZ8vU6QTDG8MoQZgyJvjK9g=; b=u8fWwSYwGIWZiOwTIA1dNjQZNz7RBxfNP22PEDYVC5SEKPiiXiHurcB5w4IWkS6yQZu4rvGOz jaxiITblE8yATWtDy9EdAsiD/hDO/Fqw98vnJkLEU9lsiW73vFtl265 X-Developer-Key: i=quic_fenglinw@quicinc.com; a=ed25519; pk=hleIDz3Unk1zeiwwOnZUjoQVMMelRancDFXg927lNjI= X-Endpoint-Received: by B4 Relay for quic_fenglinw@quicinc.com/20230725 with auth_id=68 X-Original-From: Fenglin Wu Reply-To: From: Fenglin Wu Add PM8010 regulator device nodes for sm8650-mtp board. Signed-off-by: Fenglin Wu Reviewed-by: David Collins --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 132 ++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 9d916edb1c73..e440c28e5e9f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -428,6 +428,138 @@ vreg_l3i_1p2: ldo3 { RPMH_REGULATOR_MODE_HPM>; }; }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6c_1p8>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name = "vreg_l1m_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p96: ldo7 { + regulator-name = "vreg_l7m_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_s6c_1p8>; + vdd-l5-supply = <&vreg_bob2>; + vdd-l6-supply = <&vreg_bob2>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2n_1p056: ldo2 { + regulator-name = "vreg_l2n_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + }; }; &dispcc {