diff mbox series

[2/3] clk: qcom: gcc-sm8150: Add gcc_parents_0_ao support

Message ID 20240123-gcc-ao-support-v1-2-6c18d5310874@quicinc.com
State New
Headers show
Series clk: qcom: gcc-sm8150: Add gcc_parents_0_ao support | expand

Commit Message

Satya Priya Kakitapalli Jan. 23, 2024, 4:34 p.m. UTC
Add active_only support for gcc_parents_0, this is needed because
some of the clocks under it are critical which would vote on xo
blocking the suspend.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 drivers/clk/qcom/gcc-sm8150.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Satya Priya Kakitapalli Jan. 25, 2024, 5:49 a.m. UTC | #1
On 1/23/2024 11:17 PM, Konrad Dybcio wrote:
>
>
> On 1/23/24 17:34, Satya Priya Kakitapalli wrote:
>> Add active_only support for gcc_parents_0, this is needed because
>> some of the clocks under it are critical which would vote on xo
>> blocking the suspend.
>>
>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>> ---
>
> Is there a need to keep gcc_cpuss_ahb_clk_src around? Do we do any
> ratesetting on it? Should we ever turn it off?
>

The branch clocks under gcc_cpuss_ahb_clk_src are critical clocks, which 
are running at 19.2Mhz causing vote on XO during suspend. As of now no 
rate setting is happening but this rcg is useful to get the exact rates 
from debugfs. Hence this change is needed to avoid XO shutdown issues.
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 05d115c52dfe..2a0608c5a104 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -123,6 +123,12 @@  static const struct clk_parent_data gcc_parents_0[] = {
 	{ .hw = &gpll0_out_even.clkr.hw },
 };
 
+static const struct clk_parent_data gcc_parents_0_ao[] = {
+	{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0_out_even.clkr.hw },
+};
+
 static const struct parent_map gcc_parent_map_1[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },
@@ -222,8 +228,8 @@  static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gcc_cpuss_ahb_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
+		.parent_data = gcc_parents_0_ao,
+		.num_parents = ARRAY_SIZE(gcc_parents_0_ao),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},