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Sat, 20 Jan 2024 19:19:33 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sat, 20 Jan 2024 11:19:29 -0800 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Konrad Dybcio , Conor Dooley , Johan Hovold , CC: , , , , , Krishna Kurapati Subject: [PATCH v2 3/4] arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350 Date: Sun, 21 Jan 2024 00:49:03 +0530 Message-ID: <20240120191904.15408-4-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240120191904.15408-1-quic_kriskura@quicinc.com> References: <20240120191904.15408-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: T3Feh7sHBVyrgb7xCtarXqXW2dJbb6dA X-Proofpoint-ORIG-GUID: T3Feh7sHBVyrgb7xCtarXqXW2dJbb6dA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-20_04,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 mlxscore=0 malwarescore=0 impostorscore=0 mlxlogscore=693 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401200157 For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm interrupts are used for wakeup instead of qusb2_phy irq. These targets were part of a generation that were the last ones to implement QUSB2 PHY and the design incorporated dedicated DP/DM interrupts which eventually carried forward to the newer femto based targets. Add the missing pwr_event irq for these targets. Also modify order of interrupts in accordance to bindings update. Modifying the order of these interrupts is harmless as the driver tries to get these interrupts from DT by name and not by index. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 14 +++++++++----- arch/arm64/boot/dts/qcom/sdm845.dtsi | 28 ++++++++++++++++++---------- arch/arm64/boot/dts/qcom/sm6350.dtsi | 13 ++++++++----- 3 files changed, 35 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 4d7b77a23159..80e81c4233b3 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1320,12 +1320,16 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c2244824355a..7f35c47817f4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4058,12 +4058,16 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -4109,12 +4113,16 @@ usb_2: usb@a8f8800 { <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, - <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43cffe8e1247..2fd363953bdc 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1830,12 +1830,15 @@ usb_1: usb@a6f8800 { "mock_utmi"; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>;