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b=VHMI+8Nc/F+yNgBFokRvNLqoNJii7qUbreWDepZWMZukHyzWBZbpgvaIgZj4ebtbmPNQ7eiNxSaa/jd0R0Q2r8pRxApN9poTLB7dbdtwAAFgWdg32zQ1G4np8oLUgJjn2w25GGyIB1I3Q8Wl2dNUfuetvZRxexskGjptzXlATIc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by PA4PR04MB9688.eurprd04.prod.outlook.com (2603:10a6:102:271::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.24; Fri, 19 Jan 2024 17:11:59 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::b8af:bfe5:dffd:59a9]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::b8af:bfe5:dffd:59a9%4]) with mapi id 15.20.7202.020; Fri, 19 Jan 2024 17:11:59 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v9 03/16] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Date: Fri, 19 Jan 2024 12:11:09 -0500 Message-Id: <20240119171122.3057511-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240119171122.3057511-1-Frank.Li@nxp.com> References: <20240119171122.3057511-1-Frank.Li@nxp.com> X-ClientProxiedBy: BY5PR20CA0023.namprd20.prod.outlook.com (2603:10b6:a03:1f4::36) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|PA4PR04MB9688:EE_ X-MS-Office365-Filtering-Correlation-Id: 499abe61-e0e4-4fa8-6f98-08dc1911bf0b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sjhbNHTDHEHoV3iDwDrTraJsf1Df8mqirYYkRZrhHlg1N0icNmRpxHPyEUsaA8QTKmU2qwaZNXhlclWazAdd9BRpze9B1YF50lIU8gAF1aZWtmSU32WvsD/gICeU6F4Yl4H0juJWEBRWL74UQNZPMxOD3MjJutmUyU9HPUj4gCzXBtN+RzXUNOrFPI4r/BVZd9K94NXFiUkf23lBeeQIie0IoVfXRXAgXhxEcCyjj5GoDCsQpno71wmEWDg7a43UKPwA0dque9EvHH/6eQwPEfGsANIeTKpHskIIcumpdRDgfnScFEE+SmWAUX4mjdPR4ns/dY6dGoqhOtD+pT4V3gWZRsk/fFYNTfLrz3B9n1Rk0z2BuzZ6mUrwDwOsUZ0636sFi3Zk5MYTOfV0ZyX/eFCvGiQkV7vVWhu1moZrgOTdDKfFyjGdJiZISPBYmw/Ic68g8wX3hCM36YqC0Qi7qKkzDht0Xp6o5hKyAJ2sK9ooCXU6u57MLVIAdkpwcuYhmmpOFKZVw8N/fNU3LoDugKmw1EW9eVO2rFkvRzNoTyYeHO9bFqZpNRXFFiTpQZxqOx1t+cnpf2tXjNenmHLwhUiByY+z9Kt7fd/G88lRKCk6tiRbNGRniLwOnrqs8tS2aHr/z9NWVmArd9G3x26Z1ZDnJwB84eqig9/WETRiVxT8Av8mtWwIEfCs1yLzLvNULe6d/6ctEd0kTo4sWwh2TgEv61Icv6qW9CFBDFTfBrizwb1f9jkqjAT5PNNfgKXBt8mUI4qQQ/M4LAaZwbxlhmr7/08BXlUoSLDGKbz4npSwdl0Xn6CdtL8A1b8xd1IRhYLVSm54vTnInjvKDzVZUc5vMeTFWCRT/gLnjcvVsniq5XVpyVm7WG5048Vdc0SQcQifZSYH2Fnwz7xJo9JnBIxdgFmv9CodyrR4u+z64MRqaDkEVHrqFNrNEEJ48sr5SQLIAOoyoaFuN/0YcUBLVqASEgfXM8dm+Bzn09+frmRT7i/BQu+wB9hB+SAUMW+ycoHLjITifCGQ8LVWHHObc628xzswnWURQTE6USQB39XbtzknBkUb61FJ8oCUgBApVh/1+uZ8I3z9tBIOimeRrKJIYjrgSw0D311Yq93Fjwm22ft/3gBx9/X8unTq/nUeNET9mWr7IE0Atd+PYdhqQKK5EKiTsxKlKIq8iOsFte9bZYpM8toMmXifus3mbsP5wDq7Ob6AYxx735+6co85MsCL7wk/N4B2TMpsP3AojdmlaW33ApyyoeZt2wjmyBweka3Ft6DR06Neagp2eoKoffEUN1MXJXeCxO4a2TPU16p0j29gjs0ScxdtjNG4rae4uKYG9MWH8x8khuj8NpAUrXVWmRhj/XbW95C9eyNZt/6uTRxIpiPQVgeQEEwKSZV2accPHWfEg7png8bMdL4qmZHuWM5WjlqHm2D/GHMczWFJMmxytRxE+5h/jB3oK51OyXcHEYk4TPYeXtUUv8POis+dQGrlALcN5MX4F/hGh5ksgCwwIxxfaZx/HgnUmOSzfq9tnzKfpz797C1vjvjvtCfrxKKj73WPXdnSXZ3Cux8= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 499abe61-e0e4-4fa8-6f98-08dc1911bf0b X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 17:11:59.1810 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RVvjuzmlUhH1mcYPYtobDxDYdYctLhm373XnlKZA0EnpoI3N8GUrknE0MfBHv//M2nnCLPdExlpu7MAwx16ENg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR04MB9688 Refactors the reset handling logic in the imx6 PCI driver by adding IMX6_PCIE_FLAG_HAS_*_RESET bitmask define for drvdata::flags. The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling reset. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Philipp Zabel Signed-off-by: Frank Li --- Notes: Change from v4 to v5: - Add Mani's Reviewed-by tag - Fixed MQ_EP's flags Chagne from v3 to v4: - none Change from v2 to v3: - add Philipp's Reviewed-by tag Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. Change from v1 to v2: - remove condition check before reset_control_(de)assert() because it is none ops if a NULL pointer pass down. - still keep condition check at probe to help identify dts file mismatch problem. drivers/pci/controller/dwc/pci-imx6.c | 105 ++++++++++---------------- 1 file changed, 39 insertions(+), 66 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index a33ec006660c8..eda6bc6ef80ee 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -61,6 +61,8 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) #define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3) +#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -661,18 +663,10 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { + reset_control_assert(imx6_pcie->pciephy_reset); + reset_control_assert(imx6_pcie->apps_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - reset_control_assert(imx6_pcie->pciephy_reset); - fallthrough; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); - break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, @@ -693,6 +687,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; + default: + break; } /* Some boards don't have PCIe reset GPIO. */ @@ -706,14 +702,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; + reset_control_deassert(imx6_pcie->pciephy_reset); + switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - reset_control_deassert(imx6_pcie->pciephy_reset); - break; case IMX7D: - reset_control_deassert(imx6_pcie->pciephy_reset); - /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. @@ -745,11 +737,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) usleep_range(200, 500); break; - case IMX6Q: /* Nothing to do */ - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: + default: break; } @@ -796,16 +784,11 @@ static void imx6_pcie_ltssm_enable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, IMX6Q_GPR12_PCIE_CTL_2); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_deassert(imx6_pcie->apps_reset); + default: break; } + + reset_control_deassert(imx6_pcie->apps_reset); } static void imx6_pcie_ltssm_disable(struct device *dev) @@ -819,16 +802,11 @@ static void imx6_pcie_ltssm_disable(struct device *dev) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); + default: break; } + + reset_control_assert(imx6_pcie->apps_reset); } static int imx6_pcie_start_link(struct dw_pcie *pci) @@ -1287,36 +1265,24 @@ static int imx6_pcie_probe(struct platform_device *pdev) "failed to get pcie phy\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, - "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) { - dev_err(dev, "Failed to get PCIEPHY reset control\n"); - return PTR_ERR(imx6_pcie->pciephy_reset); - } - - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) { - dev_err(dev, "Failed to get PCIE APPS reset control\n"); - return PTR_ERR(imx6_pcie->apps_reset); - } - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { + imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); + } - break; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { + imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx6_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + "Failed to get PCIEPHY reset control\n"); + } + + switch (imx6_pcie->drvdata->variant) { + case IMX7D: + if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) + imx6_pcie->controller_id = 1; default: break; } @@ -1446,13 +1412,17 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = imx6q_clks, .clks_cnt = ARRAY_SIZE(imx6q_clks), }, [IMX8MQ] = { .variant = IMX8MQ, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), @@ -1469,13 +1439,16 @@ static const struct imx6_pcie_drvdata drvdata[] = { [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHYDRV, + IMX6_PCIE_FLAG_HAS_PHYDRV | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, + .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks,