From patchwork Thu Jan 18 09:26:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 763748 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D055E200B6; Thu, 18 Jan 2024 09:26:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705570016; cv=none; b=XC68rBuYPuSgIatKrty+mhFsPmTxvClPlNcZBRiXX9SGNLD3tsQrp3UK8XCJj2hdx+Y3oE6qt9do+Lsd1PmXsP1ol0xzHf8FSI4RvYqPkbL6Nz7iL7Pu7Mh4AFD+8DHdCuQNGyIsWqt7cnHIaqfUpAqx7varXLTKS+8TdneVMbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705570016; c=relaxed/simple; bh=MCV4dqB4eVaGjG7L5iQ57P5luLp5+R3l+cbnAaRFZOs=; h=DKIM-Signature:X-CSE-ConnectionGUID:X-CSE-MsgGUID:X-IronPort-AV: X-Amp-Result:Received:Received:Received:From:To:CC:Subject:Date: Message-ID:X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding:Content-Type; b=aRv9npH8OZ8KP7XB9zTyruRtZs5NU+uOSzfYBBefDVoEwJ2Tdv49hC75eLic7DwvzL45oFeifcunTmnEG7Z933s1vzpDjmIcDNRZlwjsEHuCWPt76KJiTRqvowE7ZaAndy3Gk7qZDQV/5M4lPAhfE8kWBcnBMiPYpGuhKeP3CX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=GgaDCg1W; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="GgaDCg1W" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1705570015; x=1737106015; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MCV4dqB4eVaGjG7L5iQ57P5luLp5+R3l+cbnAaRFZOs=; b=GgaDCg1Wk8Z9YyrCzKJUpPojwY1yhwRyxxJUu5q1fMvLORml1dOpS0mb QGnd386/rcrz1vdiu5HGpDJQ6xLWKY/FPgupXJaNmvYX0QRxgZzVP441z zSL4I83GyCTvnIcsro+yRb/BxMG6+ba4HJFqsDgzVc5RQbjcEMyiZ07wo XvChRdpnjodt03vCsS3heR9fLfs7loh0CasG6tTg3vFBu5cYSbVFX7XZN T7bu/hzGac/hFD7Mfhlfktap7vXaKTPNO3UwSSNGSgr6Z1F0EIZxrbDad Csq/yRjMQsWeuph0HwmlhiwX06A9Inzz/0YC6IlXwTHYEV0PBcmNX0TdO A==; X-CSE-ConnectionGUID: /RVRxSQxQqyqw2wXGfeV8A== X-CSE-MsgGUID: 8AbJbon5RFKSA22ZDWONgQ== X-IronPort-AV: E=Sophos;i="6.05,201,1701154800"; d="scan'208";a="245651304" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Jan 2024 02:26:53 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 18 Jan 2024 02:26:52 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 18 Jan 2024 02:26:42 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , CC: , Dharma Balasubiramani Subject: [PATCH v3 3/3] dt-bindings: mfd: atmel,hlcdc: Convert to DT schema format Date: Thu, 18 Jan 2024 14:56:12 +0530 Message-ID: <20240118092612.117491-4-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240118092612.117491-1-dharma.b@microchip.com> References: <20240118092612.117491-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert the atmel,hlcdc binding to DT schema format. Adjust the clock-names property to clarify that the LCD controller expects one of these clocks (either sys_clk or lvds_pll_clk to be present but not both) along with the slow_clk and periph_clk. This alignment with the actual hardware requirements will enable accurate device tree configuration for systems using the HLCDC IP. Signed-off-by: Dharma Balasubiramani --- changelog v2 -> v3 - Rename hlcdc-display-controller and hlcdc-pwm to generic names. - Modify the description by removing the unwanted comments and '|'. - Modify clock-names simpler. v1 -> v2 - Remove the explicit copyrights. - Modify title (not include words like binding/driver). - Modify description actually describing the hardware and not the driver. - Add details of lvds_pll addition in commit message. - Ref endpoint and not endpoint-base. - Fix coding style. ... .../devicetree/bindings/mfd/atmel,hlcdc.yaml | 97 +++++++++++++++++++ .../devicetree/bindings/mfd/atmel-hlcdc.txt | 56 ----------- 2 files changed, 97 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml b/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml new file mode 100644 index 000000000000..eccc998ac42c --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCD Controller + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: + The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two + subdevices, a PWM chip and a Display Controller. + +properties: + compatible: + enum: + - atmel,at91sam9n12-hlcdc + - atmel,at91sam9x5-hlcdc + - atmel,sama5d2-hlcdc + - atmel,sama5d3-hlcdc + - atmel,sama5d4-hlcdc + - microchip,sam9x60-hlcdc + - microchip,sam9x75-xlcdc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: periph_clk + - enum: [sys_clk, lvds_pll_clk] + - const: slow_clk + + display-controller: + $ref: /schemas/display/atmel/atmel,hlcdc-display-controller.yaml + + pwm: + $ref: /schemas/pwm/atmel,hlcdc-pwm.yaml + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + + lcd_controller: lcd-controller@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + + display-controller { + compatible = "atmel,hlcdc-display-controller"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + + pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt deleted file mode 100644 index 7de696eefaed..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt +++ /dev/null @@ -1,56 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver - -Required properties: - - compatible: value should be one of the following: - "atmel,at91sam9n12-hlcdc" - "atmel,at91sam9x5-hlcdc" - "atmel,sama5d2-hlcdc" - "atmel,sama5d3-hlcdc" - "atmel,sama5d4-hlcdc" - "microchip,sam9x60-hlcdc" - "microchip,sam9x75-xlcdc" - - reg: base address and size of the HLCDC device registers. - - clock-names: the name of the 3 clocks requested by the HLCDC device. - Should contain "periph_clk", "sys_clk" and "slow_clk". - - clocks: should contain the 3 clocks requested by the HLCDC device. - - interrupts: should contain the description of the HLCDC interrupt line - -The HLCDC IP exposes two subdevices: - - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt - - a Display Controller: see ../display/atmel/hlcdc-dc.txt - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - };