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Wed, 17 Jan 2024 17:35:53 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40HHZrsd015858 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:35:53 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 17 Jan 2024 09:35:48 -0800 From: Sibi Sankar To: , , , , , , CC: , , , , , , Subject: [RFC 7/7] arm64: dts: qcom: x1e80100: Enable LLCC/DDR dvfs Date: Wed, 17 Jan 2024 23:04:58 +0530 Message-ID: <20240117173458.2312669-8-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240117173458.2312669-1-quic_sibis@quicinc.com> References: <20240117173458.2312669-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ux-GjvOXFqndpwqTxF0gfFpY0edXZbC2 X-Proofpoint-GUID: Ux-GjvOXFqndpwqTxF0gfFpY0edXZbC2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-17_10,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 mlxlogscore=556 mlxscore=0 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401170127 Enable LLCC/DDR dvfs through the Qualcomm's SCMI vendor protocol. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 48 ++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 6856a206f7fc..3dc6f32fbb4c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -329,6 +329,54 @@ scmi_dvfs: protocol@13 { reg = <0x13>; #clock-cells = <1>; }; + + scmi_vendor: protocol@80 { + reg = <0x80>; + + memlat { + #address-cells = <1>; + #size-cells = <0>; + + memory@0 { + reg = <0x0>; /* Memory Type DDR */ + freq-table-khz = <200000 4224000>; + + monitor-0 { + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>; + qcom,cpufreq-memfreq-tbl = < 999000 547000 >, + < 1440000 768000 >, + < 1671000 1555000 >, + < 2189000 2092000 >, + < 2156000 3187000 >, + < 3860000 4224000 >; + }; + + monitor-1 { + qcom,compute-mon; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>; + qcom,cpufreq-memfreq-tbl = < 1440000 200000 >, + < 2189000 768000 >, + < 2156000 1555000 >, + < 3860000 2092000 >; + }; + }; + + memory@1 { + reg = <0x1>; /* Memory Type LLCC */ + freq-table-khz = <300000 1067000>; + + monitor-0 { + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>; + qcom,cpufreq-memfreq-tbl = < 999000 300000 >, + < 1440000 466000 >, + < 1671000 600000 >, + < 2189000 806000 >, + < 2156000 933000 >, + < 3860000 1066000 >; + }; + }; + }; + }; }; };