From patchwork Thu Jan 11 10:40:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Gallais-Pou X-Patchwork-Id: 762008 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 279551549B; Thu, 11 Jan 2024 10:43:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="XWCO4PKO" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40B95I6O009306; Thu, 11 Jan 2024 11:42:32 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=Nsa2H5miBl9akiMiWy7Ow+OggKNKlHu8xqBbyIslAYs=; b=XW CO4PKOQBTgoCD3EJFTI4bCadV5m5QVMD51lDWkZFslc4Y1BTKYvTKN9q5W9VC+xH 2y/BuXAyh8iNWs2w27sD6FcX0kmnBu9esgPNsJaPD62Fbob7icV/MILfh6YYCbef sRZHfbMWpVPCcK7GmlbKKu3tdNNa9tafGu1nfSpJfjEKHXqfHlpVQI3DS5OJVwNN i8PMUeYXevEApF0ij2mH3KgX5CcHeWIWx3Inwc5t1fZmZBPHxrRcMJzRzI68cSRG oy/n4CGK076w+/Djk93lISnHUsv+8gtlMDIsE4X7wHisAZO7fYKfS89qMB1QBuAt vNytY+MKe2HifxWNnP9w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3vexpg57yg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Jan 2024 11:42:32 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3505710002A; Thu, 11 Jan 2024 11:42:32 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2CA44231504; Thu, 11 Jan 2024 11:42:32 +0100 (CET) Received: from localhost (10.252.29.122) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 11 Jan 2024 11:42:29 +0100 From: Raphael Gallais-Pou To: Yannick Fertre , Raphael Gallais-Pou , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel CC: , , , , Subject: [PATCH v2 4/6] arm64: dts: st: add ltdc support on stm32mp251 Date: Thu, 11 Jan 2024 11:40:47 +0100 Message-ID: <20240111104049.38695-5-raphael.gallais-pou@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240111104049.38695-1-raphael.gallais-pou@foss.st.com> References: <20240111104049.38695-1-raphael.gallais-pou@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-05_08,2024-01-05_01,2023-05-22_02 The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 93bc8a8908ce..064077e98dfd 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -212,6 +212,18 @@ i2c8: i2c@46040000 { status = "disabled"; }; + ltdc: display-controller@48010000 { + compatible = "st,stm32-ltdc"; + reg = <0x48010000 0x400>; + st,syscon = <&syscfg>; + interrupts = , + ; + clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>; + clock-names = "bus", "lcd"; + resets = <&rcc LTDC_R>; + status = "disabled"; + }; + sdmmc1: mmc@48220000 { compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00353180>;