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Fri, 5 Jan 2024 23:52:13 -0800 From: Petlozu Pravareshwar To: , , , , , , , , , , , , , CC: Subject: [PATCH 1/3] soc/tegra: pmc: Update address mapping sequence for PMC apertures Date: Sat, 6 Jan 2024 07:51:32 +0000 Message-ID: <20240106075134.3933491-1-petlozup@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D6:EE_|MW6PR12MB8916:EE_ X-MS-Office365-Filtering-Correlation-Id: 220909dc-9a10-4555-5a73-08dc0e8c6cda X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zqDsNiXtBXQqASj6h+ddfeoEjiCF0kNKZI1hoRyKrsvzWgXiFXVt2RB1KYf+CCL363BBer9o5Kl/g4McoBI9bOb6Vvv4u4th4rMe/9JECMkpjGnLZjptIyKIG6xVdwgwIigxbYiYSP30ZoepY6bI/+N7auNXmxFlXVmnctMmuKjbrUTFnEGYIwfvudawnGVPxsyh4M5EopLXqof+S6nAfmqNAL61uhmMm6Uv5ri/vlwAkC2gtiHALzzfBOjqO40H5GNSQYaFq90COXnhGwtkE3k4eBjknauoo2HPu6JDLFgEWf7IpY/IHupfnFD01U/Olnf5i9HIflc3UIdE4iOQvp3AJC6mXNroCyS1M7dFMEYAPTqrtteBgjILr1tPsGy7zRNFw0Q+W1nlxRfUQ0h92Wh0dhYgKALpO56DpzdK7R4XC4WUIsaeIyWqZKZT/41n51JZpbgRr/s/jIV3Lz+nGCscIy0PVdnXZCkksdeD54PJUaFCeBqIdYBWhBLY8CL8hoDN37oIuyDEy71Ye00sE9LBAhoXoVZiv0ecDlr9SXPh5E9uWbysNLEt4QgrS3UGXoRlQgZNrj7NvAAPYNyVYrpMksjVOoieYnWzLupN2B6pqluTcPrDGOlXc8OT0uNQdY2fFU46thZceKNn8nTUxv6whUuMfBcGPhNUyUVbrx7KfpIUkuF9hKT8Ndfypo1V5NQ97xX6DURUngDG8hfQKoUvXq1yi8D1pZhDfrDNC3Z3lVNRABiYBEnxfAnHTJNB X-Forefront-Antispam-Report: CIP:216.228.117.160; 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Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8916 On Tegra SoCs prior to Tegra186, PMC has single address range only. Starting from and after Tegra186, PMC has additional address ranges apart from base address range. Currently in PMC driver, we try to map these additional address ranges on all SoCs and if we fail then we assume that the range is not valid for an SoC. This change makes it more explicit on which address ranges are expected to be present on which SoCs and maps the additional address ranges only on SoCs from and after Tegra186. Signed-off-by: Petlozu Pravareshwar --- drivers/soc/tegra/pmc.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 6dfcc7f50ece..0bc983f6b088 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -384,6 +384,7 @@ struct tegra_pmc_soc { bool has_blink_output; bool has_usb_sleepwalk; bool supports_core_domain; + bool has_single_mmio_aperture; }; /** @@ -2885,31 +2886,28 @@ static int tegra_pmc_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); - if (res) { + if (pmc->soc->has_single_mmio_aperture) { + pmc->wake = base; + pmc->aotag = base; + pmc->scratch = base; + } else { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "wake"); pmc->wake = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(pmc->wake)) return PTR_ERR(pmc->wake); - } else { - pmc->wake = base; - } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); - if (res) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "aotag"); pmc->aotag = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(pmc->aotag)) return PTR_ERR(pmc->aotag); - } else { - pmc->aotag = base; - } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); - if (res) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "scratch"); pmc->scratch = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(pmc->scratch)) return PTR_ERR(pmc->scratch); - } else { - pmc->scratch = base; } pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); @@ -3300,6 +3298,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { .num_pmc_clks = 0, .has_blink_output = true, .has_usb_sleepwalk = true, + .has_single_mmio_aperture = true, }; static const char * const tegra30_powergates[] = { @@ -3361,6 +3360,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, .has_usb_sleepwalk = true, + .has_single_mmio_aperture = true, }; static const char * const tegra114_powergates[] = { @@ -3418,6 +3418,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, .has_usb_sleepwalk = true, + .has_single_mmio_aperture = true, }; static const char * const tegra124_powergates[] = { @@ -3562,6 +3563,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, .has_usb_sleepwalk = true, + .has_single_mmio_aperture = true, }; static const char * const tegra210_powergates[] = { @@ -3725,6 +3727,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, .has_usb_sleepwalk = true, + .has_single_mmio_aperture = true, }; static const struct tegra_io_pad_soc tegra186_io_pads[] = { @@ -3922,6 +3925,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .num_pmc_clks = 0, .has_blink_output = false, .has_usb_sleepwalk = false, + .has_single_mmio_aperture = false, }; static const struct tegra_io_pad_soc tegra194_io_pads[] = { @@ -4107,6 +4111,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { .num_pmc_clks = 0, .has_blink_output = false, .has_usb_sleepwalk = false, + .has_single_mmio_aperture = false, }; static const struct tegra_io_pad_soc tegra234_io_pads[] = { @@ -4235,6 +4240,7 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = { .pmc_clks_data = NULL, .num_pmc_clks = 0, .has_blink_output = false, + .has_single_mmio_aperture = false, }; static const struct of_device_id tegra_pmc_match[] = {