diff mbox series

[V2,1/3] dt-bindings: clk: sprd: Add UMS9620 support

Message ID 20240104072148.1619009-2-chunyan.zhang@unisoc.com
State New
Headers show
Series Add UMS9620 clocks driver and bindings | expand

Commit Message

Chunyan Zhang Jan. 4, 2024, 7:21 a.m. UTC 
Add UMS9620's clock compatible strings and descriptions for clock
and clock-names for UMS9620.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
 .../bindings/clock/sprd,ums512-clk.yaml       | 79 ++++++++++++++++---
 1 file changed, 68 insertions(+), 11 deletions(-)

Comments

Krzysztof Kozlowski Jan. 4, 2024, 8:48 a.m. UTC | #1 
On 04/01/2024 08:21, Chunyan Zhang wrote:
>    "#clock-cells":
>      const: 1
>  
>    clocks:
> -    minItems: 1
> -    maxItems: 4
>      description: |
>        The input parent clock(s) phandle for the clock, only list
>        fixed clocks which are declared in devicetree.
>  
> -  clock-names:

Implement my comments from v1.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
index 43d2b6c31357..dcad41a1fea7 100644
--- a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
@@ -30,25 +30,38 @@  properties:
       - sprd,ums512-mm-clk
       - sprd,ums512-mm-gate-clk
       - sprd,ums512-apapb-gate
+      - sprd,ums9620-pmu-gate
+      - sprd,ums9620-g1-pll
+      - sprd,ums9620-g5l-pll
+      - sprd,ums9620-g5r-pll
+      - sprd,ums9620-g8-pll
+      - sprd,ums9620-g9-pll
+      - sprd,ums9620-g10-pll
+      - sprd,ums9620-apapb-gate
+      - sprd,ums9620-ap-clk
+      - sprd,ums9620-apahb-gate
+      - sprd,ums9620-aon-gate
+      - sprd,ums9620-aonapb-clk
+      - sprd,ums9620-topdvfs-clk
+      - sprd,ums9620-ipaapb-gate
+      - sprd,ums9620-ipa-clk
+      - sprd,ums9620-ipaglb-gate
+      - sprd,ums9620-ipadispc-gate
+      - sprd,ums9620-pcieapb-gate
+      - sprd,ums9620-pcie-clk
+      - sprd,ums9620-mm-gate
+      - sprd,ums9620-mm-clk
+      - sprd,ums9620-dpu-vsp-gate
+      - sprd,ums9620-dpu-vsp-clk
 
   "#clock-cells":
     const: 1
 
   clocks:
-    minItems: 1
-    maxItems: 4
     description: |
       The input parent clock(s) phandle for the clock, only list
       fixed clocks which are declared in devicetree.
 
-  clock-names:
-    minItems: 1
-    items:
-      - const: ext-26m
-      - const: ext-32k
-      - const: ext-4m
-      - const: rco-100m
-
   reg:
     maxItems: 1
 
@@ -57,7 +70,43 @@  required:
   - '#clock-cells'
   - reg
 
-additionalProperties: false
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            pattern: "^sprd,ums512-.*"
+
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 4
+
+        clock-names:
+          minItems: 1
+          items:
+            - const: ext-26m
+            - const: ext-32k
+            - const: ext-4m
+            - const: rco-100m
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            pattern: "^sprd,ums9620-.*"
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 6
+
+        clock-names:
+          minItems: 1
+          maxItems: 6
+
+unevaluatedProperties: false
 
 examples:
   - |
@@ -68,4 +117,12 @@  examples:
       clock-names = "ext-26m";
       #clock-cells = <1>;
     };
+
+    aonapb_gate: clock-controller@0 {
+      compatible = "sprd,ums9620-aon-gate";
+      reg = <0x0 0x3000>;
+      clocks = <&ext_26m>, <&ext_32k>, <&rco_60m>;
+      clock-names = "ext-26m", "ext-32k", "rco-60m";
+      #clock-cells = <1>;
+    };
 ...