Message ID | 20240102140734.v4.13.Ic12bf13efe60f9ffaa444126c55a35fbf6c521cc@changeid |
---|---|
State | Accepted |
Commit | 341233b839bbd1fc47429841a0126c12d9ef271e |
Headers | show
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Improve IRQ wake capability reporting and update the cros_ec driver to use it
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diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index bbc2e9bef08da..14d58859bb55c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -762,6 +762,7 @@ ec: cros-ec@0 { interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>;
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer <markhas@chromium.org> --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 1 + 1 file changed, 1 insertion(+)