| Message ID | 20231226122113.v3.9.Ic09ebe116c18e83cc1161f4bb073fea8043f03f3@changeid |
|---|---|
| State | Superseded |
| Headers | show |
| Series | None | expand |
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 8d614ac2c58ed..335aed42dc9e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1155,6 +1155,7 @@ cros_ec: ec@0 { spi-max-frequency = <12000000>; interrupts-extended = <&pio 0 IRQ_TYPE_LEVEL_LOW>; google,cros-ec-spi-msg-delay = <500>; + wakeup-source; i2c_tunnel: i2c-tunnel0 { compatible = "google,cros-ec-i2c-tunnel";
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer <markhas@chromium.org> --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 1 + 1 file changed, 1 insertion(+)