From patchwork Fri Dec 22 17:42:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Bee X-Patchwork-Id: 757541 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B52B848788; Fri, 22 Dec 2023 17:42:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DCVK1nRD" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-33687627ad0so1708269f8f.2; Fri, 22 Dec 2023 09:42:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1703266960; x=1703871760; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UAPEf6VCNcNpH+vS9Jy42mEPmnbb20QERJ8qe9km2VY=; b=DCVK1nRDcOTtlQ4GZ8a9kVSvqA51q76OqpYuGQNhujoTa9FQDuA5sxP1IDIb/99iTC FEZpjWCCEKQ5kndlP3lTniHXh4vtvKpj6fzc1XM+CDIDmO6cp0wX1iMTaV4SwIr2oOin YA58sibHR1Ns2t5lzQSZFOnhlCFM+hvWx1QXe5OfB4V7+WVMVNx12VgMlN4XNaDMmzpB TuSqspMHRFblJHVgyJN2ik6tiZbSY4JDxdYpX0H4e1/5K/oTU7UEsD2ChrlHNianxduD CuDw/x6+nW6tS4UPJaa3zKNWHkJBMCi5iB0oPglgK098DZxIXIFZd6onmhl6CYucf7c3 2uuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703266960; x=1703871760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UAPEf6VCNcNpH+vS9Jy42mEPmnbb20QERJ8qe9km2VY=; b=ahKwLTK1Tx+veUmtwXJErGJnrckMgG7ht1Q+r3My7VDOJG5qD5plDucqtK6fi8XGl3 uhvmKGuLrGjJNgaiFoDwD8ayf2GOl+0EBmr7M/zVljwML3sWV/bR9FBGAp/NXEZzWpCL jvqg+Dd/THf4xwfE2LVfjf3FOhLdQqsWQkdfftkry6cdUnFmdv39JdmTzphaNtlg+gwm +UG+0YFZyjZaXTJUswtQlGNJ/p9/nTAeSZC1FYZ+YRUGTFzPYg/NNE3ulnzr+dnkY1X/ r7jcNfMhDfjTPRYNX0nQ28uvWWobRJrf0lHkkPFIsF6DKFDNgrLZrLEAXePjtuHXtYlo gTuA== X-Gm-Message-State: AOJu0Yxwm3tvh0DoDpahhxEGQPxTuNZ28o3Q4S2uB/7icRTSfYXC2fPU nBjnY7XbmEOTJqQDQ77YAA== X-Google-Smtp-Source: AGHT+IFGJNcPl+paeHR0rYagd/KoMDxco3f6zFqUGim2MwyHSQksycGDsS4WvE51htk1ZWVRV10PAg== X-Received: by 2002:a5d:4fcd:0:b0:336:5f15:5533 with SMTP id h13-20020a5d4fcd000000b003365f155533mr1181108wrw.54.1703266960101; Fri, 22 Dec 2023 09:42:40 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:f3ae:2788:7e03:f44]) by smtp.gmail.com with ESMTPSA id w10-20020adfec4a000000b00336670abdcasm4777116wrn.40.2023.12.22.09.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 09:42:39 -0800 (PST) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bee Subject: [PATCH v4 25/29] drm/rockchip: inno_hdmi: Add basic mode validation Date: Fri, 22 Dec 2023 18:42:16 +0100 Message-ID: <20231222174220.55249-26-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222174220.55249-1-knaerzche@gmail.com> References: <20231222174220.55249-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As per TRM this controller supports pixelclocks starting from 25 MHz. The maximum supported pixelclocks are defined by the phy configurations we have. Also it can't support modes that require doubled clocks. If the variant has a phy reference clock we can additionally validate against VESA DMT'srecommendations. Signed-off-by: Alex Bee Reviewed-by: Maxime Ripard --- changes in v2: - rename inno_mode_valid -> inno_hdmi_display_mode_valid - fixed max_tolerance calculation - use abs_diff() instead of abs() - call in inno_hdmi_display_mode_valid in atomic_check changes in v3: - collect RB changes in v4: - none drivers/gpu/drm/rockchip/inno_hdmi.c | 42 ++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index 3b76929deefe..a074451a0c49 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -26,6 +26,8 @@ #include "inno_hdmi.h" +#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U + struct inno_hdmi_phy_config { unsigned long pixelclock; u8 pre_emphasis; @@ -497,6 +499,38 @@ static int inno_hdmi_setup(struct inno_hdmi *hdmi, return 0; } +static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi, + struct drm_display_mode *mode) +{ + unsigned long mpixelclk, max_tolerance; + long rounded_refclk; + + /* No support for double-clock modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return MODE_BAD; + + mpixelclk = mode->clock * 1000; + + if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK) + return MODE_CLOCK_LOW; + + if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) + return MODE_CLOCK_HIGH; + + if (hdmi->refclk) { + rounded_refclk = clk_round_rate(hdmi->refclk, mpixelclk); + if (rounded_refclk < 0) + return MODE_BAD; + + /* Vesa DMT standard mentions +/- 0.5% max tolerance */ + max_tolerance = mpixelclk / 200; + if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance) + return MODE_NOCLOCK; + } + + return MODE_OK; +} + static void inno_hdmi_encoder_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) { @@ -529,6 +563,7 @@ inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder, struct drm_connector_state *conn_state) { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); struct drm_display_mode *mode = &crtc_state->adjusted_mode; u8 vic = drm_match_cea_mode(mode); struct inno_hdmi_connector_state *inno_conn_state = @@ -549,7 +584,8 @@ inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder, inno_conn_state->rgb_limited_range = drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED; - return 0; + return inno_hdmi_display_mode_valid(hdmi, + &crtc_state->adjusted_mode) == MODE_OK ? 0 : -EINVAL; } static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = { @@ -590,7 +626,9 @@ static enum drm_mode_status inno_hdmi_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { - return MODE_OK; + struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); + + return inno_hdmi_display_mode_valid(hdmi, mode); } static int