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[78.151.55.40]) by smtp.gmail.com with ESMTPSA id i15-20020a05600c354f00b0040d378510adsm10138520wmq.1.2023.12.22.08.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 08:54:44 -0800 (PST) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, daniel.lezcano@linaro.org, tglx@linutronix.de, conor+dt@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-team@android.com, peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com Subject: [PATCH 3/3] arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node Date: Fri, 22 Dec 2023 16:53:55 +0000 Message-ID: <20231222165355.1462740-4-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231222165355.1462740-1-peter.griffin@linaro.org> References: <20231222165355.1462740-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Peter Griffin Reviewed-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9747cb3fa03a..4b09e740b58a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -292,6 +292,26 @@ cmu_misc: clock-controller@10010000 { clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss"; }; + timer@10050000 { + compatible = "google,gs101-mct", + "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + watchdog_cl0: watchdog@10060000 { compatible = "google,gs101-wdt"; reg = <0x10060000 0x100>;