Message ID | 20231222054451.2683242-5-leong.ching.swee@intel.com |
---|---|
State | Superseded |
Headers | show |
Series | net: stmmac: Enable Per DMA Channel interrupt | expand |
> -----Original Message----- > From: Serge Semin <fancer.lancer@gmail.com> > Sent: Saturday, December 23, 2023 5:57 AM > To: Swee, Leong Ching <leong.ching.swee@intel.com> > Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>; Alexandre Torgue > <alexandre.torgue@foss.st.com>; Jose Abreu <joabreu@synopsys.com>; > David S . Miller <davem@davemloft.net>; Eric Dumazet > <edumazet@google.com>; Jakub Kicinski <kuba@kernel.org>; Paolo Abeni > <pabeni@redhat.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof > Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Conor Dooley > <conor+dt@kernel.org>; Giuseppe Cavallaro <peppe.cavallaro@st.com>; > linux-stm32@st-md-mailman.stormreply.com; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > netdev@vger.kernel.org; devicetree@vger.kernel.org; Teoh Ji Sheng > <ji.sheng.teoh@intel.com> > Subject: Re: [PATCH net-next v1 4/4] net: stmmac: Use interrupt mode > INTM=1 for per channel irq > > On Fri, Dec 22, 2023 at 01:44:51PM +0800, Leong Ching Swee wrote: > > From: Swee Leong Ching <leong.ching.swee@intel.com> > > > > Enable per DMA channel interrupt that uses shared peripheral interrupt > > (SPI), so only per channel TX and RX intr (TI/RI) are handled by TX/RX > > ISR without calling common interrupt ISR. > > > > Signed-off-by: Teoh Ji Sheng <ji.sheng.teoh@intel.com> > > Signed-off-by: Swee Leong Ching <leong.ching.swee@intel.com> > > --- > > .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 3 ++ > > .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 32 +++++++++++------- > - > > 2 files changed, 22 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > > b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > > index 207ff1799f2c..04bf731cb7ea 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > > @@ -346,6 +346,9 @@ > > /* DMA Registers */ > > #define XGMAC_DMA_MODE 0x00003000 > > #define XGMAC_SWR BIT(0) > > +#define XGMAC_DMA_MODE_INTM_MASK GENMASK(13, 12) > > +#define XGMAC_DMA_MODE_INTM_SHIFT 12 > > +#define XGMAC_DMA_MODE_INTM_MODE1 0x1 > > #define XGMAC_DMA_SYSBUS_MODE 0x00003004 > > #define XGMAC_WR_OSR_LMT GENMASK(29, 24) > > #define XGMAC_WR_OSR_LMT_SHIFT 24 > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c > > b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c > > index 3cde695fec91..dcb9f094415d 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c > > @@ -31,6 +31,13 @@ static void dwxgmac2_dma_init(void __iomem > *ioaddr, > > value |= XGMAC_EAME; > > > > writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); > > + > > + if (dma_cfg->multi_irq_en) { > > + value = readl(ioaddr + XGMAC_DMA_MODE); > > + value &= ~XGMAC_DMA_MODE_INTM_MASK; > > + value |= (XGMAC_DMA_MODE_INTM_MODE1 << > XGMAC_DMA_MODE_INTM_SHIFT); > > + writel(value, ioaddr + XGMAC_DMA_MODE); > > + } > > } > > > > static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv, @@ > > -365,19 +372,18 @@ static int dwxgmac2_dma_interrupt(struct > stmmac_priv *priv, > > } > > > > > /* TX/RX NORMAL interrupts */ > > - if (likely(intr_status & XGMAC_NIS)) { > > - if (likely(intr_status & XGMAC_RI)) { > > - u64_stats_update_begin(&rxq_stats->syncp); > > - rxq_stats->rx_normal_irq_n++; > > - u64_stats_update_end(&rxq_stats->syncp); > > - ret |= handle_rx; > > - } > > - if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { > > - u64_stats_update_begin(&txq_stats->syncp); > > - txq_stats->tx_normal_irq_n++; > > - u64_stats_update_end(&txq_stats->syncp); > > - ret |= handle_tx; > > - } > > + if (likely(intr_status & XGMAC_RI)) { > > + u64_stats_update_begin(&rxq_stats->syncp); > > + rxq_stats->rx_normal_irq_n++; > > + u64_stats_update_end(&rxq_stats->syncp); > > + ret |= handle_rx; > > + } > > + > > + if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { > > + u64_stats_update_begin(&txq_stats->syncp); > > + txq_stats->tx_normal_irq_n++; > > + u64_stats_update_end(&txq_stats->syncp); > > + ret |= handle_tx; > > Could you please clarify my comment to the original patch: > > On Fri, Aug 18, 2023 at 20:10:21PM +0300, Serge Semin wrote: > > Just curious. Is this change really necessary seeing NIS IRQ is > > unmasked and it is unmasked-OR of the RI/TI/TBU flags in the > > DMA_CHx_Status register? Moreover based on the HW manual, > > DMA_CHx_Status reflects raw IRQ flags status except NIS and AIS which > > are the masked OR of the respective flags. So AFAIU NIS will be set in > > anyway if you have RI/TI/TBU IRQs enabled. > > -Serge(y) > Thanks for your comment.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 207ff1799f2c..04bf731cb7ea 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -346,6 +346,9 @@ /* DMA Registers */ #define XGMAC_DMA_MODE 0x00003000 #define XGMAC_SWR BIT(0) +#define XGMAC_DMA_MODE_INTM_MASK GENMASK(13, 12) +#define XGMAC_DMA_MODE_INTM_SHIFT 12 +#define XGMAC_DMA_MODE_INTM_MODE1 0x1 #define XGMAC_DMA_SYSBUS_MODE 0x00003004 #define XGMAC_WR_OSR_LMT GENMASK(29, 24) #define XGMAC_WR_OSR_LMT_SHIFT 24 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 3cde695fec91..dcb9f094415d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -31,6 +31,13 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr, value |= XGMAC_EAME; writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); + + if (dma_cfg->multi_irq_en) { + value = readl(ioaddr + XGMAC_DMA_MODE); + value &= ~XGMAC_DMA_MODE_INTM_MASK; + value |= (XGMAC_DMA_MODE_INTM_MODE1 << XGMAC_DMA_MODE_INTM_SHIFT); + writel(value, ioaddr + XGMAC_DMA_MODE); + } } static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv, @@ -365,19 +372,18 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv, } /* TX/RX NORMAL interrupts */ - if (likely(intr_status & XGMAC_NIS)) { - if (likely(intr_status & XGMAC_RI)) { - u64_stats_update_begin(&rxq_stats->syncp); - rxq_stats->rx_normal_irq_n++; - u64_stats_update_end(&rxq_stats->syncp); - ret |= handle_rx; - } - if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { - u64_stats_update_begin(&txq_stats->syncp); - txq_stats->tx_normal_irq_n++; - u64_stats_update_end(&txq_stats->syncp); - ret |= handle_tx; - } + if (likely(intr_status & XGMAC_RI)) { + u64_stats_update_begin(&rxq_stats->syncp); + rxq_stats->rx_normal_irq_n++; + u64_stats_update_end(&rxq_stats->syncp); + ret |= handle_rx; + } + + if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { + u64_stats_update_begin(&txq_stats->syncp); + txq_stats->tx_normal_irq_n++; + u64_stats_update_end(&txq_stats->syncp); + ret |= handle_tx; } /* Clear interrupts */