From patchwork Fri Dec 22 05:44:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Swee, Leong Ching" X-Patchwork-Id: 757589 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F1F0C2DA; Fri, 22 Dec 2023 05:46:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cAOlTO/8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703223974; x=1734759974; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n0Gp5OLNE//xWw9yHCmOFyQdR4GTfHiilxz7KaWheEQ=; b=cAOlTO/8dciY/z1ueaoEE8SsWoNawEMFqcAOz27rb3ddjPCl/bc4KgmI hkGpQn+1q/4RJXOvFTUDz/tjONiwjOtVH6IolsthEFX0tRxkNx2EE5dPf LTdCT6g45h9T+aSi+W6kobSlnY6mjFTdS31LOjFLi81mPlWMNmuyXhEPE xe2ec1m/dM509CxiEOkyqgo1SoMsxP+MeLBgymnea0JuRYxMxbrlIaOJ4 AXAxhG6nfP520msvlAzwl+TINTROLrFzb/9ntMa5FSbMW7/Cv7HFGz667 GgFFVwJGRqYl5n+ilXUPYtQSwwKfsjqAIp5xsMbtFm6CGBKTdYqXsZc8s w==; X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="9470574" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="9470574" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 21:46:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="900324224" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="900324224" Received: from pg-esw-build.png.intel.com ([10.226.214.57]) by orsmga004.jf.intel.com with ESMTP; 21 Dec 2023 21:46:09 -0800 From: Leong Ching Swee To: Maxime Coquelin , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, Swee Leong Ching , Teoh Ji Sheng Subject: [PATCH net-next v1 3/4] net: stmmac: Add support for TX/RX channel interrupt Date: Fri, 22 Dec 2023 13:44:50 +0800 Message-Id: <20231222054451.2683242-4-leong.ching.swee@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231222054451.2683242-1-leong.ching.swee@intel.com> References: <20231222054451.2683242-1-leong.ching.swee@intel.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Swee Leong Ching Enable TX/RX channel interrupt registration for MAC that interrupts CPU through shared peripheral interrupt (SPI). Per channel interrupts and interrupt-names are registered through, Eg: 4 tx and 4 rx channels: interrupts = , , , ; ; ; ; ; interrupt-names = "dma_tx0", "dma_tx1", "dma_tx2", "dma_tx3", "dma_rx0", "dma_rx1", "dma_rx2", "dma_rx3"; Signed-off-by: Teoh Ji Sheng Signed-off-by: Swee Leong Ching --- .../ethernet/stmicro/stmmac/stmmac_platform.c | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 70eadc83ca68..f857907f13a0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -710,6 +710,8 @@ EXPORT_SYMBOL_GPL(devm_stmmac_probe_config_dt); int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + char irq_name[8]; + int i; memset(stmmac_res, 0, sizeof(*stmmac_res)); /* Get IRQ information early to have an ability to ask for deferred @@ -719,6 +721,28 @@ int stmmac_get_platform_resources(struct platform_device *pdev, if (stmmac_res->irq < 0) return stmmac_res->irq; + /* For RX Channel */ + for (i = 0; i < MTL_MAX_RX_QUEUES; i++) { + snprintf(irq_name, sizeof(irq_name), "dma_rx%i", i); + stmmac_res->rx_irq[i] = platform_get_irq_byname_optional(pdev, irq_name); + if (stmmac_res->rx_irq[i] < 0) { + if (stmmac_res->rx_irq[i] == -EPROBE_DEFER) + return -EPROBE_DEFER; + break; + } + } + + /* For TX Channel */ + for (i = 0; i < MTL_MAX_TX_QUEUES; i++) { + snprintf(irq_name, sizeof(irq_name), "dma_tx%i", i); + stmmac_res->tx_irq[i] = platform_get_irq_byname_optional(pdev, irq_name); + if (stmmac_res->tx_irq[i] < 0) { + if (stmmac_res->rx_irq[i] == -EPROBE_DEFER) + return -EPROBE_DEFER; + break; + } + } + /* On some platforms e.g. SPEAr the wake up irq differs from the mac irq * The external wake up irq can be passed through the platform code * named as "eth_wake_irq"