From patchwork Thu Dec 21 12:30:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Gallais-Pou X-Patchwork-Id: 757624 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9001F6E2D2; Thu, 21 Dec 2023 12:31:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="msAWdJtC" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BL96pjJ012155; Thu, 21 Dec 2023 13:31:26 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=33mIaakNjgGmTpsio7WUgBiZQuAUgZtT5Gp6IIaAPWw=; b=ms AWdJtCB3oyulGMALHC3STcUGYUsJ9F8FdNQAb1lfmpZpqKTWfrLUIUirxnILW/5w nCqFvgYYgaXgEMQ19brrs0AFUmGokPWTp2MR1L1Q8SDsrYh1A8xy1noumUcHOAMF MqIYfAd+oakJIWV8di0hO04m9TA40Z7C4HwDLjh7FYcfkJ9jxZUW4lrLP45bbrfR KvnTJhPBw0cd6SkfEkjPjWxglGICpeZMmrdHTOO04EiZHOpl3lc7Xw5my0dZGFdk 4ICDGVarBGf1g5/YVSbhfDx9G8KpjO6k/Ks8OXjwt3+U+rylQmMqBXHzS5M7Y+Xs 8xTEmV19dwSBKj0HwJQQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v13nhq5d3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 13:31:26 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4EBA0100053; Thu, 21 Dec 2023 13:31:25 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 42D292747C5; Thu, 21 Dec 2023 13:31:25 +0100 (CET) Received: from localhost (10.252.25.159) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Dec 2023 13:31:24 +0100 From: Raphael Gallais-Pou To: Laurent Pinchart , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Yannick Fertre , Raphael Gallais-Pou , Philippe Cornu , Philipp Zabel , Lad Prabhakar , Thierry Reding CC: , , , , Subject: [PATCH v1 7/8] arm64: dts: st: add lvds support on stm32mp253 Date: Thu, 21 Dec 2023 13:30:36 +0100 Message-ID: <20231221123037.418851-8-raphael.gallais-pou@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231221123037.418851-6-raphael.gallais-pou@foss.st.com> References: <20231221123037.418851-6-raphael.gallais-pou@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-21_05,2023-12-20_01,2023-05-22_02 This patch adds LVDS support on stm32mp253. The LVDS is used on STM32MP2 as a display interface. LVDS PLL clock is binded to the LTDC input clock. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp253.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index af48e82efe8a..bcc605e502de 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -21,3 +21,20 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; }; + +<dc { + clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>, <&lvds 0>; + clock-names = "bus", "lcd", "lvds"; +}; + +&rifsc { + lvds: lvds@48060000 { + #clock-cells = <0>; + compatible = "st,stm32-lvds"; + reg = <0x48060000 0x2000>; + clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names = "pclk", "ref"; + resets = <&rcc LVDS_R>; + status = "disabled"; + }; +};