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([178.197.218.27]) by smtp.gmail.com with ESMTPSA id u25-20020a17090617d900b00a2328f844d2sm2823925eje.85.2023.12.18.07.07.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 07:07:03 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] arm64: dts: qcom: x1e80100: align mem timer size cells with bindings Date: Mon, 18 Dec 2023 16:06:56 +0100 Message-Id: <20231218150656.72892-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ARMv7 memory mapped architected timer bindings expect MMIO sizes up to 32-bit. Keep 64-bit addressing but change the size of memory mapping to 32-bit (size-cells=1) and adjust the ranges to match this. This fixes dtbs_check warnings like: x1e80100-qcp.dtb: timer@17800000: #size-cells:0:0: 1 was expected Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index fd09fbc7d8e7..be1285d9919e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3417,12 +3417,12 @@ timer@17800000 { reg = <0 0x17800000 0 0x1000>; #address-cells = <2>; - #size-cells = <2>; - ranges; + #size-cells = <1>; + ranges = <0 0 0 0 0x20000000>; frame@17801000 { - reg = <0 0x17801000 0 0x1000>, - <0 0x17802000 0 0x1000>; + reg = <0 0x17801000 0x1000>, + <0 0x17802000 0x1000>; interrupts = , ; @@ -3431,7 +3431,7 @@ frame@17801000 { }; frame@17803000 { - reg = <0 0x17803000 0 0x1000>; + reg = <0 0x17803000 0x1000>; interrupts = ; @@ -3441,7 +3441,7 @@ frame@17803000 { }; frame@17805000 { - reg = <0 0x17805000 0 0x1000>; + reg = <0 0x17805000 0x1000>; interrupts = ; @@ -3451,7 +3451,7 @@ frame@17805000 { }; frame@17807000 { - reg = <0 0x17807000 0 0x1000>; + reg = <0 0x17807000 0x1000>; interrupts = ; @@ -3461,7 +3461,7 @@ frame@17807000 { }; frame@17809000 { - reg = <0 0x17809000 0 0x1000>; + reg = <0 0x17809000 0x1000>; interrupts = ; @@ -3471,7 +3471,7 @@ frame@17809000 { }; frame@1780b000 { - reg = <0 0x1780b000 0 0x1000>; + reg = <0 0x1780b000 0x1000>; interrupts = ; @@ -3481,7 +3481,7 @@ frame@1780b000 { }; frame@1780d000 { - reg = <0 0x1780d000 0 0x1000>; + reg = <0 0x1780d000 0x1000>; interrupts = ;