From patchwork Thu Dec 14 06:28:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 754624 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="JlpUzm31" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A4261BB; Wed, 13 Dec 2023 22:30:33 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE6RaTm011805; Thu, 14 Dec 2023 06:30:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=97iArE/7fSpUEFf1nWhOfrrjPwTNcjVGC7vrxk+Z5PY=; b=Jl pUzm31S7Tc8NMcwNCtiSDsmK9h61Ll0sLrc8OuUF+mU6ZCEgB9S+ZEU8iGoSUvZC 4TzbOd/NTK64Q9tU7fYHrtBepBTTbMbMUYcusUTAm8EvA2xoqntHy/uNmkUhy3E8 /ajeO0Usc6n2SET0qhgcpnSUICW80iWVc9MczDGKrtPAtLXpzxGWyFlQxkJD9LOK mUzdqhF20654njCEvVa7fWbQxKB+RZMa0uKA3bcVXdkq8K5AQR824qirfPbIRuBG s7vEtZKH6Wx7m6Vw3Kk5v7GfqZbf9tZgzoUJqXP+1d/iYIJhDp9iQVYLVJEzDFcV 13G9HCtm8DnJGSAKnLHg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyqgt0jeq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:30:24 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE6UNiV018007 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:30:23 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:30:15 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 10/10] arm64: dts: qcom: ipq5332: Enable PCIe phys and controllers Date: Thu, 14 Dec 2023 11:58:47 +0530 Message-ID: <20231214062847.2215542-11-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9xfHIffaGkkmrwGB9V7CzBTBrvmfquZJ X-Proofpoint-ORIG-GUID: 9xfHIffaGkkmrwGB9V7CzBTBrvmfquZJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=827 mlxscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 Enable the PCIe controller and PHY nodes for RDP 441. Signed-off-by: Praveenkumar I --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..83eca8435cff 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -62,4 +62,78 @@ data-pins { bias-pull-up; }; }; + + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio37"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio39"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio46"; + function = "pcie1_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio48"; + function = "pcie1_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default>; + + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default>; + + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + status = "okay"; };