@@ -1472,7 +1472,7 @@ gfx3d1: iommu@7d00000 {
qcom,ncb = <3>;
};
- pcie: pci@1b500000 {
+ pcie: pcie@1b500000 {
compatible = "qcom,pcie-apq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
@@ -98,7 +98,7 @@ flash@0 {
};
};
- pci@40000000 {
+ pcie@40000000 {
status = "okay";
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
@@ -417,7 +417,7 @@ restart@4ab000 {
reg = <0x4ab000 0x4>;
};
- pcie0: pci@40000000 {
+ pcie0: pcie@40000000 {
compatible = "qcom,pcie-ipq4019";
reg = <0x40000000 0xf1d>,
<0x40000f20 0xa8>,
@@ -1076,7 +1076,7 @@ sata_phy: sata-phy@1b400000 {
status = "disabled";
};
- pcie0: pci@1b500000 {
+ pcie0: pcie@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
0x1b502000 0x80
@@ -1127,7 +1127,7 @@ pcie0: pci@1b500000 {
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
};
- pcie1: pci@1b700000 {
+ pcie1: pcie@1b700000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b700000 0x1000
0x1b702000 0x80
@@ -1178,7 +1178,7 @@ pcie1: pci@1b700000 {
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
};
- pcie2: pci@1b900000 {
+ pcie2: pcie@1b900000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b900000 0x1000
0x1b902000 0x80
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct node name for the controller instances. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-)