From patchwork Thu Nov 30 16:16:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 748675 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="Z7NP5Rpa" Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67AB110DB; Thu, 30 Nov 2023 08:18:43 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 82E6DC0299; Thu, 30 Nov 2023 17:18:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361121; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=FWmRsZBPeCXE6vjeXku2odgdbDKh17lvQDeEaVqehTE=; b=Z7NP5RpaTw3MIjxwsmnte30n+WOZ2rGGmHahxck8cwPNrw08b52Rkwm5hjXPiAOeYPjTvI gh01KjutQ82a4X6+C9kv/iDqpeGApPUh6QIgTSaqg/I9SNNH8j/Vcc6kk5ii3BCpR5gd3H 67idbuqWEGB6TIinyJDNNcPQbyQoqMykezHtkwfxaCb5u60QvQC1xqMP5RAU58mx8LfxBP JypY490vgvfxyGH166OnCwPSufOp6MGj+1reSjsmYb3VUloppm6688tJNeGdHzwisCXZqM eBhXkYvT4e0bbnC9Ligf8hN6bRJvzPBG4mfCMn+2WQMuPJ+lVAejPxXB3KYvlA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 05/14] arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL OSM-S board Date: Thu, 30 Nov 2023 17:16:05 +0100 Message-ID: <20231130161657.556483-6-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 From: Frieder Schrempf These signals are actively driven by the SoC or by the onboard transceiver. There's no need to enable the internal pull resistors and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 0730c22e5b6b9..1dd03ef0a7835 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -313,19 +313,19 @@ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; };