From patchwork Fri Nov 24 10:06:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 746893 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kf6i08KD" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E57A8D73; Fri, 24 Nov 2023 02:09:05 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AO5qG2V016718; Fri, 24 Nov 2023 10:08:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=aUVfSE7o29E/Ln05PzcZvHLfe4Lx0nIxOUnYZnZypjY=; b=kf6i08KDApRbTqFq2bB4h9zqh6TOSaFBJPsYsyWL45xExvTFcNPobqgnKKKxe9sIpnHA XnaWijs3Ngg9MEsQzxLk6leeiQbmILM7KRluPN9ri6TEH8CLJU73SbFnMRc04gaAHW5K hvZMPBKD8mGQjp8p7dE8dzrkOh9jabD5B62aYN5y6FDvCkZy4a1a3T2mqXRcjjGxuK6H v8C3fKBnAkOkVMIwD6qD998L30yMnED+9Zv22+BRivgtLDL0y41YAbeDkymVGH7ffH3u v2PNa80iNHF5Fs5A5oxWEvnKEekZo2ung5/Yj02YgrplSDm2Vp0Df7bte5u8OI5RrkKZ ww== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uj7gjt09u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Nov 2023 10:08:54 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AOA8rAx021312 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Nov 2023 10:08:53 GMT Received: from blr-ubuntu-253.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 24 Nov 2023 02:08:46 -0800 From: Sibi Sankar To: , , , , , , , CC: , , , , , , , , , , , , Sibi Sankar Subject: [PATCH V3 2/5] dt-bindings: arm-smmu: Add compatible for X1E80100 SoC Date: Fri, 24 Nov 2023 15:36:05 +0530 Message-ID: <20231124100608.29964-3-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231124100608.29964-1-quic_sibis@quicinc.com> References: <20231124100608.29964-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8qzI-eJINC1nvXaA1yJjxtT3YR_CML_b X-Proofpoint-GUID: 8qzI-eJINC1nvXaA1yJjxtT3YR_CML_b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_15,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=902 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311240079 From: Rajendra Nayak Add the SoC specific compatible for X1E80100 implementing arm,mmu-500. Signed-off-by: Rajendra Nayak Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Reviewed-by: Krzysztof Kozlowski --- v3: * Pickup Rbs. Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index aa9e1c0895a5..7ae4f65fe236 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -56,6 +56,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,x1e80100-smmu-500 - const: qcom,smmu-500 - const: arm,mmu-500 @@ -475,6 +476,7 @@ allOf: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,x1e80100-smmu-500 then: properties: clock-names: false