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Tue, 14 Nov 2023 02:19:56 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id v9-20020a5d43c9000000b0032da022855fsm7419675wrr.111.2023.11.14.02.19.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 02:19:56 -0800 (PST) From: Neil Armstrong Date: Tue, 14 Nov 2023 11:19:51 +0100 Subject: [PATCH 2/2] pmdomain: amlogic: meson-ee-pwrc: add support for G12A ISP power domain Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-topic-amlogic-upstream-isp-pmdomain-v1-2-f01e6fca67a0@linaro.org> References: <20231114-topic-amlogic-upstream-isp-pmdomain-v1-0-f01e6fca67a0@linaro.org> In-Reply-To: <20231114-topic-amlogic-upstream-isp-pmdomain-v1-0-f01e6fca67a0@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Ulf Hansson Cc: Daniel Scally , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add entries for the ISP power domain found in the Amlogic G12B SoC Signed-off-by: Neil Armstrong --- drivers/pmdomain/amlogic/meson-ee-pwrc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pmdomain/amlogic/meson-ee-pwrc.c b/drivers/pmdomain/amlogic/meson-ee-pwrc.c index 0dd71cd814c5..cba216a2175e 100644 --- a/drivers/pmdomain/amlogic/meson-ee-pwrc.c +++ b/drivers/pmdomain/amlogic/meson-ee-pwrc.c @@ -47,6 +47,8 @@ #define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) #define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) +#define G12A_HHI_ISP_MEM_PD_REG0 (0x45 << 2) +#define G12A_HHI_ISP_MEM_PD_REG1 (0x46 << 2) struct meson_ee_pwrc; struct meson_ee_pwrc_domain; @@ -115,6 +117,13 @@ static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { .iso_mask = BIT(16) | BIT(17), }; +static struct meson_ee_pwrc_top_domain g12a_pwrc_isp = { + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, + .sleep_mask = BIT(18) | BIT(19), + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, + .iso_mask = BIT(18) | BIT(19), +}; + /* Memory PD Domains */ #define VPU_MEMPD(__reg) \ @@ -231,6 +240,11 @@ static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(31, 0) }, }; +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_isp[] = { + { G12A_HHI_ISP_MEM_PD_REG0, GENMASK(31, 0) }, + { G12A_HHI_ISP_MEM_PD_REG0, GENMASK(31, 0) }, +}; + #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name = __name, \ @@ -269,6 +283,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, pwrc_ee_is_powered_off), + [PWRC_G12A_ISP_ID] = TOP_PD("ISP", &g12a_pwrc_isp, g12a_pwrc_mem_isp, + pwrc_ee_is_powered_off), }; static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {