From patchwork Mon Nov 13 18:56:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 744227 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C89B122303 for ; Mon, 13 Nov 2023 18:56:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="E6788382" Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 951C210F4 for ; Mon, 13 Nov 2023 10:56:17 -0800 (PST) Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6cd09f51fe0so3065326a34.1 for ; Mon, 13 Nov 2023 10:56:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1699901776; x=1700506576; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=P1Ce5IgwMvaim1HBsUAsZyKlbiwCpIsxUYaeOyQhPqA=; b=E6788382qkXFobeCoIuA2W52m3f90tJGT8QZFRT8hxu/1vyfF8XYidxVUmCeldbKCE OC9l8N7vgHupqomYjNldHhj1PaAOn/Vn7GFWglPeod8uKLUJD12FiwLCKwz+2dbqO//R jfxElnGe4jigDYinoa9zoCrtXU4HMzilLZT0U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699901776; x=1700506576; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=P1Ce5IgwMvaim1HBsUAsZyKlbiwCpIsxUYaeOyQhPqA=; b=JthvgzVvzvSBf+cLXG0RRjTjW1Z4VtN0riQYPGIr6aL/39YrvuIVE9sNQxuD/aDzOV vHRbiqOP+qv7qAe8YFguJtUz41GY52FPefT8LeNXPCGi5xo6q4SW10ZZ7HbwjyuuJZUt qR0hBCVkP31368e5VUDM00cX8WTibibn1n1WWtajUVLVKiLnMJST/1mjHvQ/+CMzVL35 utMuiPyo/JyraMtNPqByMk+AWOlMyJBne+vFbR+tTbA0DrQRD4aOlGawPPi9IZjHcT3S pzVgsfobzu19b4spj/2Gz+D1/shrOvA83fb3HoOo15yctsSfX9UCwlu5I5Ply5ZXDMph rWTw== X-Gm-Message-State: AOJu0YwySwquRkZuY1Vnt0VHsxDDsASetUXYosrgJIBpxFSTWPe/0YSV YJHWoKrzKkuboOpzdHsuqla19A== X-Google-Smtp-Source: AGHT+IErjmkWNhMqOy4IBy2kxoU1xMlFc0sDuIp2ZP8QVqKkUQerQ7XTcAR6YKddBeX2rXPtd+IUIw== X-Received: by 2002:a9d:7e91:0:b0:6bf:1e78:cc52 with SMTP id m17-20020a9d7e91000000b006bf1e78cc52mr8877640otp.25.1699901776721; Mon, 13 Nov 2023 10:56:16 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id b187-20020a6334c4000000b0056b27af8715sm4366421pga.43.2023.11.13.10.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 10:56:16 -0800 (PST) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Jim Quinlan , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v8 1/2] dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" Date: Mon, 13 Nov 2023 13:56:05 -0500 Message-Id: <20231113185607.1756-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231113185607.1756-1-james.quinlan@broadcom.com> References: <20231113185607.1756-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver to deliberately place the RC HW one of three CLKREQ# modes. The "brcm,clkreq-mode" property allows the user to override the default setting. If this property is omitted, the default mode shall be "default". Signed-off-by: Jim Quinlan --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..22491f7f8852 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,24 @@ properties: aspm-no-l0s: true + brcm,clkreq-mode: + description: A string that determines the operating + clkreq mode of the PCIe RC HW with respect to controlling the refclk + signal. There are three different modes -- "safe", which drives the + refclk signal unconditionally and will work for all devices but does + not provide any power savings; "no-l1ss" -- which provides Clock + Power Management, L0s, and L1, but cannot provide L1 substate (L1SS) + power savings. If the downstream device connected to the RC is L1SS + capable AND the OS enables L1SS, all PCIe traffic may abruptly halt, + potentially hanging the system; "default" -- which provides L0s, L1, + and L1SS, but not compliant to provide Clock Power Management; + specifically, may not be able to meet the T_CLRon max timing of 400ns + as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI + Express Mini CEM 2.1 specification. This situation is atypical and + should happen only with older devices. + $ref: /schemas/types.yaml#/definitions/string + enum: [ safe, no-l1ss, default ] + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to