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Sun, 05 Nov 2023 09:45:08 -0800 (PST) Received: from [127.0.0.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id t10-20020a05600c198a00b004064ac107cfsm9553346wmq.39.2023.11.05.09.45.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 09:45:07 -0800 (PST) From: Bryan O'Donoghue Date: Sun, 05 Nov 2023 17:45:03 +0000 Subject: [PATCH v3 4/6] media: qcom: camss: Add sc8280xp resource details Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231105-b4-camss-sc8280xp-v3-4-4b3c372ff0f4@linaro.org> References: <20231105-b4-camss-sc8280xp-v3-0-4b3c372ff0f4@linaro.org> In-Reply-To: <20231105-b4-camss-sc8280xp-v3-0-4b3c372ff0f4@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-26615 This commit describes the hardware layout for the sc8280xp for the following hardware blocks: - 4 x VFE, 4 RDI per VFE - 4 x VFE Lite, 4 RDI per VFE - 4 x CSID - 4 x CSID Lite - 4 x CSI PHY Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.c | 383 ++++++++++++++++++++++++++++++ 1 file changed, 383 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 8778fdc1ee342..51619842f3925 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -941,6 +941,374 @@ static const struct resources_icc icc_res_sm8250[] = { }, }; +static const struct camss_subdev_resources csiphy_res_sc8280xp[] = { + /* CSIPHY0 */ + { + .regulators = {}, + .clock = { "csiphy0", "csiphy0_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY1 */ + { + .regulators = {}, + .clock = { "csiphy1", "csiphy1_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY2 */ + { + .regulators = {}, + .clock = { "csiphy2", "csiphy2_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY3 */ + { + .regulators = {}, + .clock = { "csiphy3", "csiphy3_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" }, + .ops = &csiphy_ops_3ph_1_0 + }, +}; + +static const struct camss_subdev_resources csid_res_sc8280xp[] = { + /* CSID0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe0_csid_src", "vfe0_csid", "cphy_rx_src", + "vfe0_cphy_rx", "vfe0_src", "vfe0", "vfe0_axi" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .ops = &csid_ops_gen2 + }, + /* CSID1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe1_csid_src", "vfe1_csid", "cphy_rx_src", + "vfe1_cphy_rx", "vfe1_src", "vfe1", "vfe1_axi" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .ops = &csid_ops_gen2 + }, + /* CSID2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe2_csid_src", "vfe2_csid", "cphy_rx_src", + "vfe2_cphy_rx", "vfe2_src", "vfe2", "vfe2_axi" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .ops = &csid_ops_gen2 + }, + /* CSID3 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe3_csid_src", "vfe3_csid", "cphy_rx_src", + "vfe3_cphy_rx", "vfe3_src", "vfe3", "vfe3_axi" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 } }, + .reg = { "csid3" }, + .interrupt = { "csid3" }, + .ops = &csid_ops_gen2 + }, + /* CSID_LITE0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe_lite0_csid_src", "vfe_lite0_csid", + "cphy_rx_src", "vfe_lite0_cphy_rx", "vfe_lite0_src", + "vfe_lite0" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, }, + .reg = { "csid0_lite" }, + .interrupt = { "csid0_lite" }, + .is_lite = true, + .ops = &csid_ops_gen2 + }, + /* CSID_LITE1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe_lite1_csid_src", "vfe_lite1_csid", + "cphy_rx_src", "vfe_lite1_cphy_rx", "vfe_lite1_src", + "vfe_lite1" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, }, + .reg = { "csid1_lite" }, + .interrupt = { "csid1_lite" }, + .is_lite = true, + .ops = &csid_ops_gen2 + }, + /* CSID_LITE2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe_lite2_csid_src", "vfe_lite2_csid", + "cphy_rx_src", "vfe_lite2_cphy_rx", "vfe_lite2_src", + "vfe_lite2" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, }, + .reg = { "csid2_lite" }, + .interrupt = { "csid2_lite" }, + .is_lite = true, + .ops = &csid_ops_gen2 + }, + /* CSID_LITE3 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe_lite3_csid_src", "vfe_lite3_csid", + "cphy_rx_src", "vfe_lite3_cphy_rx", "vfe_lite3_src", + "vfe_lite3" }, + .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, }, + .reg = { "csid3_lite" }, + .interrupt = { "csid3_lite" }, + .is_lite = true, + .ops = &csid_ops_gen2 + } +}; + +static const struct camss_subdev_resources vfe_res_sc8280xp[] = { + /* IFE0 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe0_src", "vfe0", "vfe0_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .pd_name = "ife0", + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE1 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe1_src", "vfe1", "vfe1_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .pd_name = "ife1", + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE2 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe2_src", "vfe2", "vfe2_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg = { "vfe2" }, + .interrupt = { "vfe2" }, + .pd_name = "ife2", + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* VFE3 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe3_src", "vfe3", "vfe3_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg = { "vfe3" }, + .interrupt = { "vfe3" }, + .pd_name = "ife3", + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE_LITE_0 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe_lite0_src", "vfe_lite0" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE_LITE_1 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe_lite1_src", "vfe_lite1" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* IFE_LITE_2 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe_lite2_src", "vfe_lite2" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000, }, }, + .reg = { "vfe_lite2" }, + .interrupt = { "vfe_lite2" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + }, + /* VFE_LITE_3 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "gcc_axi_sf", "slow_ahb_src", + "cpas_ahb", "camnoc_axi", "camnoc_axi_src", + "vfe_lite3_src", "vfe_lite3" }, + .clock_rate = { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 80000000 }, + { 0 }, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg = { "vfe_lite3" }, + .interrupt = { "vfe_lite3" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + }, +}; + +static const struct resources_icc icc_res_sc8280xp[] = { + { + .name = "cam_ahb", + .icc_bw_tbl.avg = 150000, + .icc_bw_tbl.peak = 300000, + }, + { + .name = "cam_hf_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "cam_sf_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "cam_sf_icp_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -1824,12 +2192,27 @@ static const struct camss_resources sm8250_resources = { .vfe_num = ARRAY_SIZE(vfe_res_8250), }; +static const struct camss_resources sc8280xp_resources = { + .version = CAMSS_8280XP, + .pd_name = "top", + .csiphy_res = csiphy_res_sc8280xp, + .csid_res = csid_res_sc8280xp, + .ispif_res = NULL, + .vfe_res = vfe_res_sc8280xp, + .icc_res = icc_res_sc8280xp, + .icc_path_num = ARRAY_SIZE(icc_res_sc8280xp), + .csiphy_num = ARRAY_SIZE(csiphy_res_sc8280xp), + .csid_num = ARRAY_SIZE(csid_res_sc8280xp), + .vfe_num = ARRAY_SIZE(vfe_res_sc8280xp), +}; + static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, + { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { } };