From patchwork Mon Oct 16 06:43:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 734691 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23F5214294 for ; Mon, 16 Oct 2023 06:44:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="HWHu2zDI" Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47AC6AD; Sun, 15 Oct 2023 23:43:59 -0700 (PDT) X-UUID: 607210686bef11eea33bb35ae8d461a2-20231016 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=969Bqk5Iw5hnZHxjN31bqZT8jd0W5KgkuSGYWGgbXPA=; b=HWHu2zDIFgQnCphnXLyr4+o+oM/C/sxAYofP2PSuzBOhJRcL6Zix+Yxa1GJXzG4J3hzH6dqy7NOBJwJZcJBb+AdIUWLU7OglhVSx/gSQF62BaUfSAzBHgIj1NwfakgfixmM8rXePUsJPDqoMHbQveXsZZoqeBZ4tBNOF1J7qLhs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32, REQID:b36fece1-e16b-4860-b757-7d1f310e4325, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9, CLOUDID:8f36d6f0-9a6e-4c39-b73e-f2bc08ca3dc5, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 607210686bef11eea33bb35ae8d461a2-20231016 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2089451445; Mon, 16 Oct 2023 14:43:55 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 16 Oct 2023 14:43:54 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 16 Oct 2023 14:43:53 +0800 From: Yunfei Dong To: =?utf-8?q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert CC: Chen-Yu Tsai , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , Yunfei Dong , , , , , , Subject: [PATCH 7/7] media: mediatek: vcodec: Setting the supported vp9 profile for each platform Date: Mon, 16 Oct 2023 14:43:46 +0800 Message-ID: <20231016064346.31451-7-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231016064346.31451-1-yunfei.dong@mediatek.com> References: <20231016064346.31451-1-yunfei.dong@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net The supported format type of different platforms are not the same. Need to set the supported profile according to the chip name. Signed-off-by: Yunfei Dong Reviewed-by: Sebastian Fricke --- .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index 02985184fa0f..ae181498c3c3 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -109,7 +109,8 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE, .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0, .def = V4L2_MPEG_VIDEO_VP9_PROFILE_0, - .max = V4L2_MPEG_VIDEO_VP9_PROFILE_3, + .max = V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .menu_skip_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_1), }, .codec_type = V4L2_PIX_FMT_VP9_FRAME, }, @@ -630,6 +631,20 @@ static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, }; } +static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (ctx->dev->chip_name) { + case MTK_VDEC_MT8188: + case MTK_VDEC_MT8195: + cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2; + break; + default: + cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_1; + break; + }; +} + static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { @@ -656,6 +671,11 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, mtk_v4l2_vdec_dbg(3, ctx, "h265 supported profile: %lld %lld", cfg->max, cfg->menu_skip_mask); break; + case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: + mtk_vcodec_dec_fill_vp9_profile(cfg, ctx); + mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported profile: %lld %lld", cfg->max, + cfg->menu_skip_mask); + break; default: break; };