From patchwork Sat Oct 7 15:48:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 730708 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A788C30F90; Sat, 7 Oct 2023 15:49:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Y88vhYm8" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7950DF; Sat, 7 Oct 2023 08:49:22 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 397FNpes016503; Sat, 7 Oct 2023 15:49:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=k1NDylHKSYeI5UYWFLGJ4cy2Wuo0jxcJAkPAngncU30=; b=Y88vhYm8L8sT4GZgtMHPj0b390RYdw28BmS7jaytKvqYV1R/OGkUuPoS5+rOFsexLa4S NXUSpYsFWjfzsvtpwhz+cZd/hfYlhZneqEeKhVAUD16TNwumxlcIEYAm22+0RN9lrz6d sdAw8OjDriwU3rAes5VBhS5fRjOgVJhW/eh6Km4q0jML8yhXt+lBaIi2fEzMYHhwvHT+ UU5uMtNBS68SbDWOFH6t32VL+dXpS8SmUDB1ZyZ9zUOKxKDhCRC8kywgGk8nY6dA/PER AT03kt5rkLTsimsPlcibWYtcUrqkVVxpoZhCvshKhIuP6iJqfCAtE2gJw1WIKfC+DGvC 1A== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3tjyqc8x78-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 07 Oct 2023 15:49:14 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 397FnDlG003220 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 7 Oct 2023 15:49:13 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Sat, 7 Oct 2023 08:49:07 -0700 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , Johan Hovold CC: , , , , , , , , , Krishna Kurapati Subject: [PATCH v13 07/10] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Date: Sat, 7 Oct 2023 21:18:03 +0530 Message-ID: <20231007154806.605-8-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231007154806.605-1-quic_kriskura@quicinc.com> References: <20231007154806.605-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: RaxiRJJM0eIqYDaqgQSyQ3fvy4IzSN_H X-Proofpoint-ORIG-GUID: RaxiRJJM0eIqYDaqgQSyQ3fvy4IzSN_H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-07_12,2023-10-06_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=886 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310070143 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net QCOM SoC SA8295P's tertiary quad port controller supports 2 HS+SS ports and 2 HS only ports. Add support for configuring PWR_EVENT_IRQ's for all the ports during suspend/resume. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/dwc3-qcom.c | 35 ++++++++++++++++++++++++++++------- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 651b9775a0c2..dbd4239e61c9 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -37,7 +37,11 @@ #define PIPE3_PHYSTATUS_SW BIT(3) #define PIPE_UTMI_CLK_DIS BIT(8) -#define PWR_EVNT_IRQ_STAT_REG 0x58 +#define PWR_EVNT_IRQ1_STAT_REG 0x58 +#define PWR_EVNT_IRQ2_STAT_REG 0x1dc +#define PWR_EVNT_IRQ3_STAT_REG 0x228 +#define PWR_EVNT_IRQ4_STAT_REG 0x238 + #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) @@ -107,6 +111,19 @@ struct dwc3_qcom { int num_ports; }; +/* + * Currently non-multiport controller have only one PWR_EVENT_IRQ register, + * but multiport controllers like SA8295 contain upto 4 of them. + */ +#define NUM_PWR_EVENT_STAT_REGS 4 + +static u32 pwr_evnt_irq_stat_reg_offset[NUM_PWR_EVENT_STAT_REGS] = { + PWR_EVNT_IRQ1_STAT_REG, + PWR_EVNT_IRQ2_STAT_REG, + PWR_EVNT_IRQ3_STAT_REG, + PWR_EVNT_IRQ4_STAT_REG, +}; + static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -446,9 +463,11 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) if (qcom->is_suspended) return 0; - val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); - if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) - dev_err(qcom->dev, "HS-PHY not in L2\n"); + for (i = 0; i < qcom->num_ports; i++) { + val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]); + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) + dev_err(qcom->dev, "HS-PHY not in L2\n"); + } for (i = qcom->num_clocks - 1; i >= 0; i--) clk_disable_unprepare(qcom->clks[i]); @@ -494,9 +513,11 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); /* Clear existing events from PHY related to L2 in/out */ - dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, - PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); - + for (i = 0; i < qcom->num_ports; i++) { + dwc3_qcom_setbits(qcom->qscratch_base, + pwr_evnt_irq_stat_reg_offset[i], + PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); + } qcom->is_suspended = false; return 0;