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Thu, 5 Oct 2023 22:25:32 +0300 (IDT) From: Tomer Maimon To: , , , , , , , , , , , , CC: , , , , Tomer Maimon Subject: [PATCH v5 3/3] usb: chipidea: Add support for NPCM Date: Thu, 5 Oct 2023 22:25:29 +0300 Message-ID: <20231005192529.162785-4-tmaimon77@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20231005192529.162785-1-tmaimon77@gmail.com> References: <20231005192529.162785-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NotSetDelaration: True X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: HK3PEPF0000021C:EE_|TY0PR03MB6906:EE_ X-MS-Office365-Filtering-Correlation-Id: fbb5b761-b2d9-4e77-1a79-08dbc5d8d8e6 X-MS-Exchange-SenderADCheck: 0 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QWV4nT2hWi6CTQBXqMik4gOCHG1mYbhxPsdnslqhbMfxRjSrhWjKkIkTm9j7KHA5p7FZYT8v2omCBWeSWdI39fMwDoDztT53QbM4cvSQHN/qW+zFOgsLVyzxnrBvXbJYzJ6MrOFLoStkc9ORzHnI+FPCKjZYkijl2clMMold4R4DvtiOYMZ6O96edmvzEzafxl5FM8cdK9cD11ZquLPFvgcGhRmJe/9YisninXLWgRWi+NmwUMVLHgah9LRmNxQEwVsmOtStEhlskbTNRVE4cnDmgJxBW/Hyq/o8ubjOc+LdTLRQcbX9JUVVQj83wxM1Rm7fmw5VaCz1S5CRq3lM4YB7eUSXmYGpSXo9mS8PqkX0vkhGtiOAPtyHOWXKixU0QFoTD2At5XvFYJvkU2AsN/AE/aDFO3JAeksYyDMltgWvCktZbJMG/pIp9giMQ2N9A7unOfhKvHi3/NQjwaxdaD2mCqcTAS/wv8KRNaVslSdWR1QpNLWCU8zzOaTqB9OUwBRxMMSIllK2mj2M3iEAoNqdifvzIMQvOR4ezNrNcSwtEBR8/gub7V8jUlSiZlWMJticLDm+qKOtOM782QPlF/MXAZkVpAnVe4JarmPq0jfw06PHtWexzQPeL4pf1pa75lr1t+RGHCelbQmMzroI4/xPGNmU6CrEzDSy45WggWhlpPEucUvjYsM6WZu8LHLBf7gtct40tdo2lSLgtxXt7mrUUpgaHh3DRSCruM8Vg/jUap5ne5TXR4IN89HIrdYKddBpTUQ5BFOkHx5drodwT7aHXrEfklCLciK6xP1VOUba9rbqh0tqn9GoVU/Hp06HYxqQkkPNCdkPXKd2ZLabR7WKP1apHhnL8WHpIsm6SymM4bZ1ZcCs58K9Dmu98ywZ/FEu1PzHjhBHF1PCW+X5w+TgUWYy0AZ+sZFvIPlg1SKt3uZzzv9w6EtyHuiXwHOpA4jJouokQXyRXRFGjTJgTomdoGLGASATEyaT4vik0Rc= X-Forefront-Antispam-Report: CIP:211.75.126.7; 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Ip=[211.75.126.7]; Helo=[NTHCCAS01.nuvoton.com] X-MS-Exchange-CrossTenant-AuthSource: HK3PEPF0000021C.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY0PR03MB6906 X-Spam-Status: No, score=0.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FORGED_GMAIL_RCVD,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,NML_ADSP_CUSTOM_MED, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add Nuvoton NPCM BMC SoCs support to USB ChipIdea driver. NPCM SoC include ChipIdea IP block that used for USB device controller mode. Signed-off-by: Tomer Maimon Acked-by: Peter Chen --- drivers/usb/chipidea/Kconfig | 4 + drivers/usb/chipidea/Makefile | 1 + drivers/usb/chipidea/ci_hdrc_npcm.c | 114 ++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/usb/chipidea/ci_hdrc_npcm.c diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig index c815824a0b2d..bab45bc62361 100644 --- a/drivers/usb/chipidea/Kconfig +++ b/drivers/usb/chipidea/Kconfig @@ -43,6 +43,10 @@ config USB_CHIPIDEA_MSM tristate "Enable MSM hsusb glue driver" if EXPERT default USB_CHIPIDEA +config USB_CHIPIDEA_NPCM + tristate "Enable NPCM hsusb glue driver" if EXPERT + default USB_CHIPIDEA + config USB_CHIPIDEA_IMX tristate "Enable i.MX USB glue driver" if EXPERT depends on OF diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile index 71afeab97e83..718cb24603dd 100644 --- a/drivers/usb/chipidea/Makefile +++ b/drivers/usb/chipidea/Makefile @@ -13,6 +13,7 @@ ci_hdrc-$(CONFIG_USB_OTG_FSM) += otg_fsm.o obj-$(CONFIG_USB_CHIPIDEA_GENERIC) += ci_hdrc_usb2.o obj-$(CONFIG_USB_CHIPIDEA_MSM) += ci_hdrc_msm.o +obj-$(CONFIG_USB_CHIPIDEA_NPCM) += ci_hdrc_npcm.o obj-$(CONFIG_USB_CHIPIDEA_PCI) += ci_hdrc_pci.o obj-$(CONFIG_USB_CHIPIDEA_IMX) += usbmisc_imx.o ci_hdrc_imx.o obj-$(CONFIG_USB_CHIPIDEA_TEGRA) += ci_hdrc_tegra.o diff --git a/drivers/usb/chipidea/ci_hdrc_npcm.c b/drivers/usb/chipidea/ci_hdrc_npcm.c new file mode 100644 index 000000000000..37b64a3dbd96 --- /dev/null +++ b/drivers/usb/chipidea/ci_hdrc_npcm.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2023 Nuvoton Technology corporation. + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ci.h" + +struct npcm_udc_data { + struct platform_device *ci; + struct clk *core_clk; + struct ci_hdrc_platform_data pdata; +}; + +static int npcm_udc_notify_event(struct ci_hdrc *ci, unsigned event) +{ + struct device *dev = ci->dev->parent; + + switch (event) { + case CI_HDRC_CONTROLLER_RESET_EVENT: + /* clear all mode bits */ + hw_write(ci, OP_USBMODE, 0xffffffff, 0x0); + break; + default: + dev_dbg(dev, "unknown ci_hdrc event\n"); + break; + } + + return 0; +} + +static int npcm_udc_probe(struct platform_device *pdev) +{ + int ret; + struct npcm_udc_data *ci; + struct platform_device *plat_ci; + struct device *dev = &pdev->dev; + + ci = devm_kzalloc(&pdev->dev, sizeof(*ci), GFP_KERNEL); + if (!ci) + return -ENOMEM; + platform_set_drvdata(pdev, ci); + + ci->core_clk = devm_clk_get_optional(dev, NULL); + if (IS_ERR(ci->core_clk)) + return PTR_ERR(ci->core_clk); + + ret = clk_prepare_enable(ci->core_clk); + if (ret) + return dev_err_probe(dev, ret, "failed to enable the clock: %d\n", ret); + + ci->pdata.name = dev_name(dev); + ci->pdata.capoffset = DEF_CAPOFFSET; + ci->pdata.flags = CI_HDRC_REQUIRES_ALIGNED_DMA | + CI_HDRC_FORCE_VBUS_ACTIVE_ALWAYS; + ci->pdata.phy_mode = USBPHY_INTERFACE_MODE_UTMI; + ci->pdata.notify_event = npcm_udc_notify_event; + + plat_ci = ci_hdrc_add_device(dev, pdev->resource, pdev->num_resources, + &ci->pdata); + if (IS_ERR(plat_ci)) { + ret = PTR_ERR(plat_ci); + dev_err(dev, "failed to register HDRC NPCM device: %d\n", ret); + goto clk_err; + } + + pm_runtime_no_callbacks(dev); + pm_runtime_enable(dev); + + return 0; + +clk_err: + clk_disable_unprepare(ci->core_clk); + return ret; +} + +static int npcm_udc_remove(struct platform_device *pdev) +{ + struct npcm_udc_data *ci = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + ci_hdrc_remove_device(ci->ci); + clk_disable_unprepare(ci->core_clk); + + return 0; +} + +static const struct of_device_id npcm_udc_dt_match[] = { + { .compatible = "nuvoton,npcm750-udc", }, + { .compatible = "nuvoton,npcm845-udc", }, + { } +}; +MODULE_DEVICE_TABLE(of, npcm_udc_dt_match); + +static struct platform_driver npcm_udc_driver = { + .probe = npcm_udc_probe, + .remove = npcm_udc_remove, + .driver = { + .name = "npcm_udc", + .of_match_table = npcm_udc_dt_match, + }, +}; + +module_platform_driver(npcm_udc_driver); + +MODULE_DESCRIPTION("NPCM USB device controller driver"); +MODULE_AUTHOR("Tomer Maimon "); +MODULE_LICENSE("GPL v2");