From patchwork Tue Oct 3 04:43:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 729026 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6998645 for ; Tue, 3 Oct 2023 04:45:09 +0000 (UTC) Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B9A0D3 for ; Mon, 2 Oct 2023 21:45:04 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-690b7cb71aeso353763b3a.0 for ; Mon, 02 Oct 2023 21:45:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1696308303; x=1696913103; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2RNpF/CWjVyq2jAidq9g4JrMuQdRaRtl2xGmvH6ydPA=; b=k+aamnU/xegf8QrsvQn3Zw1j4q9ezVrwK1rVrMFr7XkcotzI/pPuXKnYpK1EqDGU2h RvxDMo/Ep+4NfuvVSiQR6nlvHH59F1zaA52tTIjmJPK7BisPHXE+L9B/zImzwXHMIlb2 KTxxOPg4nXnIA2AEpcJIvVk4yHZLi8f5MgBola0dDllGo72ktzHcbxs63d2Spiuk/qCU ygDiJBEyj9erreX9XaP2YyV8nTDn41bsLuwrh99pRhjyGroPQc5UPwOMkk6sXWpUcKUp GuntxnKYnQrndQAExRzyBGPlMhCzoiCpGRs8/cYUKLNXcM3n4tSnS6aFCCUZJbd23szf p9OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696308303; x=1696913103; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2RNpF/CWjVyq2jAidq9g4JrMuQdRaRtl2xGmvH6ydPA=; b=E4JW3sRU6AS3uK8q4IeNEKm5EBE9zUtx3mZwzF5IjasFFaLQFzQXoH4vu2whzZlh5h 12cpMJEcPaEyDyvvweMvdXAWzZsedmVqoSm/u4PJ/Iyn4y+fOdKXrmFGhvC5GNj5jekp AlBwJvaqSlzocW3ICIzepgKMQZeW/8v9YyUsejyv8p32LLkom//560LyXwN004SjHW0r nBZqxByryeLLOkelAt9u3SKuTa6mDQbZ5ct6KrRm66fWZ+IWGB25DSEV2n917SKwgOr4 xz43B2N87aNHO3/X6OSVGpcqwQ8u6xkZVmj/G8RAoBKECYcZRmsifLc4GhffqnWb/YV1 HvXA== X-Gm-Message-State: AOJu0YyaWkL5Oz1uyyL8S2wYA1eH2gUZJvBYIYj/lk+w7sY8UmBTattN BcoJsSSEwt6SGXbAUXUDZkBmCA== X-Google-Smtp-Source: AGHT+IG/Wp0pe3mxTS0qRgMZuqi2/oc2AwsUXkS16/9T8AJqBsR6vFzMhpHcjJWRci/pF5CllP/yVg== X-Received: by 2002:a05:6a00:b55:b0:68f:cb69:8e66 with SMTP id p21-20020a056a000b5500b0068fcb698e66mr2518288pfo.15.1696308303308; Mon, 02 Oct 2023 21:45:03 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.132]) by smtp.gmail.com with ESMTPSA id h9-20020aa786c9000000b0068e49cb1692sm346421pfo.1.2023.10.02.21.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 21:45:02 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v10 06/15] irqchip/riscv-intc: Add support for RISC-V AIA Date: Tue, 3 Oct 2023 10:13:54 +0530 Message-Id: <20231003044403.1974628-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231003044403.1974628-1-apatel@ventanamicro.com> References: <20231003044403.1974628-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller We add support for #1 and #2 described above in the RISC-V intc driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 34 ++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e8d01b14ccdd..bab536bbaf2c 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include static struct irq_domain *intc_domain; @@ -30,6 +31,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) generic_handle_domain_irq(intc_domain, cause); } +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi = csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, + topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +49,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_clear(CSR_IE, BIT(d->hwirq)); } static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_set(CSR_IE, BIT(d->hwirq)); } static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +131,20 @@ static struct fwnode_handle *riscv_intc_hwnode(void) static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs = riscv_isa_extension_available(NULL, SxAIA) ? + 64 : BITS_PER_LONG; - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, + intc_domain = irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } - rc = set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc = set_handle_irq(&riscv_intc_aia_irq); + else + rc = set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +152,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", + nr_irqs, riscv_isa_extension_available(NULL, SxAIA) ? + " using AIA" : ""); return 0; }