From patchwork Tue Sep 19 10:43:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 724464 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD4B91D6AF for ; Tue, 19 Sep 2023 10:47:56 +0000 (UTC) Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9370513E for ; Tue, 19 Sep 2023 03:47:53 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-68fac16ee5fso4698948b3a.1 for ; Tue, 19 Sep 2023 03:47:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1695120473; x=1695725273; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+wGYSKJ+LCREMj4ZZPD+f0Pekeht6gsRJzvaQhiRmgU=; b=i/Zi+RnMMWwqHRAi5eyMP8BEVDcrPYf6JAK/AvjUUIaJi3DI5FDbihVH9zRZfmzg4e c0uKqm5hQ647b9LcFMrrH6CZ0bh7lj15045qIHBjV4M6EoVUfTAcGdS25jBeNvjr9Lts oURKuZIgyAimVdfq3aXOPfCN95FkoWyfs7PZU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695120473; x=1695725273; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+wGYSKJ+LCREMj4ZZPD+f0Pekeht6gsRJzvaQhiRmgU=; b=XBUIvrKXdfDcnTxw6g4ZRpcLjGVhwUZKc7Xcogfy4jpfUZMPl761sbHbsiHlX7AhYX RNbPJQr6QdBIDM6BPsy53WMGCj55mTsfjE+3K5ZOkJVRAwIu+lH0tP7MP8xADFwUfPnv PpgNR5xWAxzwDPPyyH/Ja2lu294qfG+0sFuLDtC4Fbqo4DSUa3ZkvyvuhjMPvZO8iPwE E8qJ+83O2WNn/uFwUTmUSPY0BNq3A9b502J3FAHJkAm3Joqv0J/+/Y0syfI6TGmo6oxh sUOBejGD4UtILy++VehxnzN93Zp342YqDzvPFM0+640RXlCAKWpWTyITyfe93b/x+wfL lWZA== X-Gm-Message-State: AOJu0YyRXJID9UCYmP+OgW5lq89t2Jje7KOPM4/24+VJ80ENqcz25s2N 3IhH5XC/3hyfZ5sJJhnV5Ujbvg== X-Google-Smtp-Source: AGHT+IEmKxPbrVXvTZMke/E8nxAuI6FZj0Gbgh2pZBbB90/74RtIhcOTn7X3KsvzvN92RJtv02gvbg== X-Received: by 2002:a05:6a21:6d88:b0:15b:2125:890f with SMTP id wl8-20020a056a216d8800b0015b2125890fmr7209933pzb.37.1695120472905; Tue, 19 Sep 2023 03:47:52 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:40a:900d:e731:5a43]) by smtp.gmail.com with ESMTPSA id c10-20020a170902d48a00b001bc445e249asm6719578plg.124.2023.09.19.03.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 03:47:52 -0700 (PDT) From: Chen-Yu Tsai To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Mark Brown Cc: Chen-Yu Tsai , Zhiyong Tao , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 11/12] regulator: mt6358: Add supply names for MT6366 regulators Date: Tue, 19 Sep 2023 18:43:54 +0800 Message-ID: <20230919104357.3971512-12-wenst@chromium.org> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog In-Reply-To: <20230919104357.3971512-1-wenst@chromium.org> References: <20230919104357.3971512-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net The DT bindings for MT6366 regulator defines the supply names for the PMIC. Add support for them by adding .supply_name field settings for each regulator. The buck regulators each have their own supply whose name can be derived from the regulator name. The LDOs have shared supplies. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- Changes since v2: none Changes since v1: - Replaced underscores in supply names with hyphens - Reflowed a couple macros for readability drivers/regulator/mt6358-regulator.c | 77 +++++++++++++--------------- 1 file changed, 37 insertions(+), 40 deletions(-) diff --git a/drivers/regulator/mt6358-regulator.c b/drivers/regulator/mt6358-regulator.c index 4e7891e514b6..58ee93aa2a34 100644 --- a/drivers/regulator/mt6358-regulator.c +++ b/drivers/regulator/mt6358-regulator.c @@ -140,6 +140,7 @@ struct mt6358_regulator_info { [MT6366_ID_##vreg] = { \ .desc = { \ .name = #vreg, \ + .supply_name = "vsys-" match, \ .of_match = of_match_ptr(match), \ .ops = &mt6358_volt_range_ops, \ .type = REGULATOR_VOLTAGE, \ @@ -162,10 +163,11 @@ struct mt6358_regulator_info { .modeset_mask = BIT(_modeset_shift), \ } -#define MT6366_LDO(match, vreg, volt_ranges, enreg, enbit, vosel, vosel_mask) \ +#define MT6366_LDO(match, vreg, volt_ranges, supply, enreg, enbit, vosel, vosel_mask) \ [MT6366_ID_##vreg] = { \ .desc = { \ .name = #vreg, \ + .supply_name = supply, \ .of_match = of_match_ptr(match), \ .ops = &mt6358_volt_table_ops, \ .type = REGULATOR_VOLTAGE, \ @@ -186,12 +188,12 @@ struct mt6358_regulator_info { .qi = BIT(15), \ } -#define MT6366_LDO1(match, vreg, min, max, step, \ - _da_vsel_reg, _da_vsel_mask, \ - vosel, vosel_mask) \ +#define MT6366_LDO1(match, vreg, supply, min, max, step, \ + _da_vsel_reg, _da_vsel_mask, vosel, vosel_mask) \ [MT6366_ID_##vreg] = { \ .desc = { \ .name = #vreg, \ + .supply_name = supply, \ .of_match = of_match_ptr(match), \ .ops = &mt6358_volt_range_ops, \ .type = REGULATOR_VOLTAGE, \ @@ -211,11 +213,11 @@ struct mt6358_regulator_info { .qi = BIT(0), \ } -#define MT6366_REG_FIXED(match, vreg, \ - enreg, enbit, volt) \ +#define MT6366_REG_FIXED(match, vreg, supply, enreg, enbit, volt) \ [MT6366_ID_##vreg] = { \ .desc = { \ .name = #vreg, \ + .supply_name = supply, \ .of_match = of_match_ptr(match), \ .ops = &mt6358_volt_fixed_ops, \ .type = REGULATOR_VOLTAGE, \ @@ -584,57 +586,52 @@ static const struct mt6358_regulator_info mt6366_regulators[] = { 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8), MT6366_BUCK("vs1", VS1, 1000000, 2587500, 12500, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8), - MT6366_REG_FIXED("vrf12", VRF12, - MT6358_LDO_VRF12_CON0, 0, 1200000), - MT6366_REG_FIXED("vio18", VIO18, - MT6358_LDO_VIO18_CON0, 0, 1800000), - MT6366_REG_FIXED("vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000), - MT6366_REG_FIXED("vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000), - MT6366_REG_FIXED("vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000), - MT6366_REG_FIXED("vaux18", VAUX18, - MT6358_LDO_VAUX18_CON0, 0, 1800000), - MT6366_REG_FIXED("vbif28", VBIF28, - MT6358_LDO_VBIF28_CON0, 0, 2800000), - MT6366_REG_FIXED("vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000), - MT6366_REG_FIXED("va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000), - MT6366_REG_FIXED("vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000), - MT6366_REG_FIXED("vaud28", VAUD28, - MT6358_LDO_VAUD28_CON0, 0, 2800000), - MT6366_LDO("vdram2", VDRAM2, vdram2, + MT6366_REG_FIXED("vrf12", VRF12, "vs2-ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000), + MT6366_REG_FIXED("vio18", VIO18, "vs1-ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000), + MT6366_REG_FIXED("vfe28", VFE28, "vsys-ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000), + MT6366_REG_FIXED("vcn28", VCN28, "vsys-ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000), + MT6366_REG_FIXED("vxo22", VXO22, "vsys-ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000), + MT6366_REG_FIXED("vaux18", VAUX18, "vsys-ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000), + MT6366_REG_FIXED("vbif28", VBIF28, "vsys-ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000), + MT6366_REG_FIXED("vio28", VIO28, "vsys-ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000), + MT6366_REG_FIXED("va12", VA12, "vs2-ldo2", MT6358_LDO_VA12_CON0, 0, 1200000), + MT6366_REG_FIXED("vrf18", VRF18, "vs1-ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000), + MT6366_REG_FIXED("vaud28", VAUD28, "vsys-ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000), + MT6366_LDO("vdram2", VDRAM2, vdram2, "vs2-ldo1", MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10), - MT6366_LDO("vsim1", VSIM1, vsim, + MT6366_LDO("vsim1", VSIM1, vsim, "vsys-ldo1", MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00), - MT6366_LDO("vibr", VIBR, vibr, + MT6366_LDO("vibr", VIBR, vibr, "vsys-ldo3", MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00), - MT6366_LDO("vusb", VUSB, vusb, + MT6366_LDO("vusb", VUSB, vusb, "vsys-ldo1", MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700), - MT6366_LDO("vefuse", VEFUSE, vefuse, + MT6366_LDO("vefuse", VEFUSE, vefuse, "vs1-ldo1", MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00), - MT6366_LDO("vmch", VMCH, vmch_vemc, + MT6366_LDO("vmch", VMCH, vmch_vemc, "vsys-ldo2", MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700), - MT6366_LDO("vemc", VEMC, vmch_vemc, + MT6366_LDO("vemc", VEMC, vmch_vemc, "vsys-ldo3", MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700), - MT6366_LDO("vcn33", VCN33, vcn33, + MT6366_LDO("vcn33", VCN33, vcn33, "vsys-ldo3", MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300), - MT6366_LDO("vmc", VMC, vmc, + MT6366_LDO("vmc", VMC, vmc, "vsys-ldo2", MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00), - MT6366_LDO("vsim2", VSIM2, vsim, + MT6366_LDO("vsim2", VSIM2, vsim, "vsys-ldo2", MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00), - MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18, + MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18, "vs1-ldo1", MT6358_LDO_VCN18_CON0, 0, MT6358_VCN18_ANA_CON0, 0xf00), - MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18, + MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18, "vs1-ldo1", MT6358_LDO_VM18_CON0, 0, MT6358_VM18_ANA_CON0, 0xf00), - MT6366_LDO("vmddr", VMDDR, mt6366_vmddr, + MT6366_LDO("vmddr", VMDDR, mt6366_vmddr, "vs2-ldo1", MT6358_LDO_VMDDR_CON0, 0, MT6358_VMDDR_ANA_CON0, 0xf00), - MT6366_LDO1("vsram-proc11", VSRAM_PROC11, 500000, 1293750, 6250, + MT6366_LDO1("vsram-proc11", VSRAM_PROC11, "vs2-ldo3", 500000, 1293750, 6250, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f), - MT6366_LDO1("vsram-others", VSRAM_OTHERS, 500000, 1293750, 6250, + MT6366_LDO1("vsram-others", VSRAM_OTHERS, "vs2-ldo3", 500000, 1293750, 6250, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f), - MT6366_LDO1("vsram-gpu", VSRAM_GPU, 500000, 1293750, 6250, + MT6366_LDO1("vsram-gpu", VSRAM_GPU, "vs2-ldo3", 500000, 1293750, 6250, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f), - MT6366_LDO1("vsram-proc12", VSRAM_PROC12, 500000, 1293750, 6250, + MT6366_LDO1("vsram-proc12", VSRAM_PROC12, "vs2-ldo3", 500000, 1293750, 6250, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f), - MT6366_LDO1("vsram-core", VSRAM_CORE, 500000, 1293750, 6250, + MT6366_LDO1("vsram-core", VSRAM_CORE, "vs2-ldo3", 500000, 1293750, 6250, MT6358_LDO_VSRAM_CORE_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON5, 0x7f), };