From patchwork Fri Sep 15 20:19:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 723352 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26F5B18E09 for ; Fri, 15 Sep 2023 20:20:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6FBD0C433C7; Fri, 15 Sep 2023 20:20:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694809204; bh=+pZKuROLmBdIrfo491pE/sQfj9kOoSQEDuZxmmaZMuY=; h=From:To:Cc:Subject:Date:From; b=pLIVKgF4dnRVJLeCqx8HYhHUY8SvSrIXIlPr7f47FMgsP0kEtUjfk18z2d64X5aA9 hsMUFqw/E+wJRjGSBFKA0Z4SsbvhvBlLGFxPRI4rZEXPAKqoIhNyI4cMsI4k3zMDVt +UwrH+gWKrI9VGHWH4ME8qqnwVyj26I750hiwNzIayYdenFvazGKdWFKRx8nNiCNLT OvOCZ7niYRmduAyapBZt/nFg3cbk4FPzF7Og+VkH3ATNbr2HCTruw/TJTvvC+bHgxT 8ugq+sbEaBMmqWPuknw6UpgxLNKXs0O6qgXmW8D+8+qoLXA985FF3VeRiIHygwT7Dc lYKBGYj+eyqaQ== Received: (nullmailer pid 4184984 invoked by uid 1000); Fri, 15 Sep 2023 20:20:00 -0000 From: Rob Herring To: Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] dt-bindings: riscv: cpus: Add missing additionalProperties on interrupt-controller node Date: Fri, 15 Sep 2023 15:19:36 -0500 Message-Id: <20230915201946.4184468-1-robh@kernel.org> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The "interrupt-controller" CPU child node is missing constraints on extra properties. Add "additionalProperties: false" to fix this. Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 38c0b5213736..97e8441eda1c 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -91,6 +91,7 @@ properties: interrupt-controller: type: object + additionalProperties: false description: Describes the CPU's local interrupt controller properties: