From patchwork Wed Sep 6 04:56:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 720520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50B00EB8FB3 for ; Wed, 6 Sep 2023 04:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237436AbjIFE5I (ORCPT ); Wed, 6 Sep 2023 00:57:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237143AbjIFE5G (ORCPT ); Wed, 6 Sep 2023 00:57:06 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A1DB1A8; Tue, 5 Sep 2023 21:56:59 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3864e4pw002049; Wed, 6 Sep 2023 04:56:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=xviZKReq4zDE2JhRl1oGDrwUnAPFf/yLSLWZLxQdxw4=; b=pi3r1dNf9ylgQdTIJNgsg+Z5NX48llMDC6jvptNVHH3nT7A+B3WRUoAROLyNxsF125Ry YrMAhOBGoIvxM5heAph7tvaiFPlGEOLoC5e4mkUZbbb5sxrdbbPbFG+QQftpnJqs23Zl NdxzO01F6y+Hf3cqbnT5fUn+b0OU2aJjChJ5jfwSs3391Yv1+3O0bsKJwYdNvfgf9x8J Bsycowc0zBYXqKyMt8ai1/pVMA97vG2nVETh/R0v1uqFOLosHDjWQjBMMWkEAvFQDbN8 rEDLWnwnbvs115ABlxodO+jTKNhlA46C5WmCHrBuh1VlB6gxZcXDBI9OtVEZ7RRN1q0E 3w== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3sxha305hg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Sep 2023 04:56:46 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3864ujxS012990 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Sep 2023 04:56:45 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 5 Sep 2023 21:56:40 -0700 From: Kathiravan Thirumoorthy Date: Wed, 6 Sep 2023 10:26:21 +0530 Subject: [PATCH RESEND 2/7] clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks MIME-Version: 1.0 Message-ID: <20230904-gpll_cleanup-v1-2-de2c448f1188@quicinc.com> References: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> In-Reply-To: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Michael Turquette , "Stephen Boyd" , Sricharan Ramabadhran , Anusha Rao , Devi Priya , , , , CC: Kathiravan Thirumoorthy X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693976190; l=2158; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=HVjEqzCxHlgD0fXslB0uy/S3ENoNzNcmNC724Whk4mM=; b=1vX+cnkV5VpYAkdPhvurtQ7cRw67isA44GDXxcKhFJX4LO6uWUhw0NZbLemyAYaZ6C6oFIIye vKA48rPvyqhBUrtNhjdB9LPxNtHnu9qQbbujB+hl362dq8+0Q06oZnS X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: -NuN0a5ig6j7liZsuySEgvVlRr7Su51l X-Proofpoint-GUID: -NuN0a5ig6j7liZsuySEgvVlRr7Su51l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-05_13,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 mlxlogscore=908 impostorscore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 suspectscore=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309060044 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org GPLL, UBI32 PLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL clocks. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq6018.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 6120fbbc5de0..d6be70538566 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -72,7 +72,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -86,7 +85,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -130,7 +128,6 @@ static struct clk_alpha_pll_postdiv ubi32_pll = { &ubi32_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -161,7 +158,6 @@ static struct clk_alpha_pll_postdiv gpll6 = { &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -192,7 +188,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -243,7 +238,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -274,7 +268,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { &nss_crypto_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, };